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34 .807ireless important notice dear customer, as from august 2 nd 2008, the wireless operations of nxp have moved to a new company, st-nxp wireless. as a result, the following changes are applicable to the attached document. company name - philips semiconductors is replaced with st-nxp wireless . copyright - the copyright notice at the botto m of each page ?? koninklijke philips electronics n.v. 200x. all rights reserved?, shall now read: ?? st-nxp wireless 200x - all rights reserved?. web site - http://www.semiconductors.philips.com is replaced with http://www.stnwireless.com contact information - the list of sales offices previous ly obtained by sending an email to sales.addresses@www.semiconductors.philips.com , is now found at http://www.stnwireless.com under contacts. if you have any questions related to the document, please contact our nearest sales office. thank you for your cooperation and understanding. st-nxp wireless 34 .807ireless www.stnwireless.com
isp1160 embedded universal serial bus host controller rev. 05 24 december 2004 product data 1. general description the isp1160 is an embedded universal serial bus (usb) host controller (hc) that complies with universal serial bus speci?cation rev. 2.0 , supporting data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s). the isp1160 provides two downstream ports. each downstream port has an overcurrent (oc) detection input pin and power supply switching control output pin. the downstream ports for the hc can be connected with any usb compliant usb devices and usb hubs that have usb upstream ports. the isp1160 is well suited for embedded systems and portable devices that require a usb host. the isp1160 brings high ?exibility to the systems that have it built-in. for example, a system that has the isp1160 built-in allows it to be connected to a device that has a usb upstream port, such as a usb printer, usb camera, usb keyboard, usb mouse, among others. 2. features n complies with universal serial bus speci?cation rev. 2.0 n supports data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s) n adapted from open host controller interface speci?cation for usb release 1.0a n selectable one or two downstream ports for hc n high-speed parallel interface to most of the generic microprocessors and reduced instruction set computer (risc) processors such as: u hitachi ? superh? sh-3 and sh-4 u mips-based? risc u arm7?, arm9?, and strongarm ? n maximum 15 mbyte/s data transfer rate between the microprocessor and the hc n supports single-cycle and burst mode dma operations n built-in fifo buffer ram for the hc (4 kbytes) n endpoints with double buffering to increase throughput and ease real-time data transfer for isochronous (iso) transactions n 6 mhz crystal oscillator with integrated pll for low emi n built-in software selectable internal 15 k w pull-down resistors for hc downstream ports n dedicated pins for suspend sensing output and wake-up control input for ?exible applications n operation at either + 5 v or + 3.3 v power supply voltage n operating temperature range from - 40 cto + 85 c n available in two lqfp64 packages (sot314-2 and sot414-1).
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 2 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. applications n personal digital assistant (pda) n digital camera n third-generation (3-g) phone n set-top box (stb) n information appliance (ia) n photo printer n mp3 jukebox n game console. 4. ordering information [1] improvement in performance as compared to isp1160bd. [2] improvement in performance as compared to isp1160bm. table 1: ordering information type number package name description version isp1160bd lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 isp1160bd/01 [1] isp1160bm lqfp64 plastic low pro?le quad ?at package; 64 leads; body 7 7 1.4 mm sot414-1 isp1160bm/01 [2]
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors isp1160 embedded usb host controller 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 05 24 december 2004 3 of 88 5. block diagram fig 1. block diagram. 57 004aaa059 16 15 k w gnd microprocessor bus interface clock recovery power switching overcurrent detection usb transceiver usb transceiver pll clock recovery host controller voltage regulator internal supply internal reset 3.3 v v cc power-on reset v reg(3v3) v hold 1 dgnd 7 1, 8, 15, 18, 35, 45, 62 10 itl0 (ping ram) itl1 (pong ram) isp1160 h_wakeup h_psw1_n 46 43 19 v hold 2 24 58 2 to 7, 9 to 14, 16, 17, 63, 64 40 42 33 22 21 23 59 27 34 25 29 32 56 n.c. 20, 26, 30, 31, 36, 38, 41, 48, 49, 61 44 47 54 55 50 51 52 53 xtal1 xtal2 h_psw2_n h_oc1_n h_oc2_n usb bus downstream ports h_dm1 h_dp1 h_dm2 h_dp2 h_suspend ndp_sel d0 to d15 rd_n eot dreq int reset_n atl ram 6 mhz 4 agnd cs_n wr_n a0 dack_n
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 4 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description (1) isp1160/01 is the marking on the ic for the isp1160bd/01 and 1160/01 is the marking on the ic for the isp1160bm/01. fig 2. pin con?guration lqfp64. isp1160bd isp1160bm isp1160/01 1160/01 (1) 004aaa060 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 n.c. h_psw2_n h_psw1_n dgnd 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 d1 d0 dgnd n.c. low_pw a0 v reg(3v3) agnd v cc h_oc2_n h_oc1_n h_dp2 h_dm2 h_dp1 h_dm1 n.c. 49 dgnd d2 d3 d4 d5 d6 dgnd d8 d10 d11 d7 d9 d13 dgnd d14 d15 dgnd v hold 1 n.c. rd_n wr_n v hold2 d12 cs_n n.c. n.c. int test_high dack_n n.c. dreq reset_n n.c. dgnd eot ndp_sel xtal2 xtal1 h_suspend h_wakeup test_low n.c. test_low n.c. table 2: pin description lqfp64 symbol [1] pin type description dgnd 1 - digital ground d2 2 i/o bit 2 of bidirectional data; slew-rate controlled; ttl input; three-state output d3 3 i/o bit 3 of bidirectional data; slew-rate controlled; ttl input; three-state output
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 5 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. d4 4 i/o bit 4 of bidirectional data; slew-rate controlled; ttl input; three-state output d5 5 i/o bit 5 of bidirectional data; slew-rate controlled; ttl input; three-state output d6 6 i/o bit 6 of bidirectional data; slew-rate controlled; ttl input; three-state output d7 7 i/o bit 7 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 8 - digital ground d8 9 i/o bit 8 of bidirectional data; slew-rate controlled; ttl input; three-state output d9 10 i/o bit 9 of bidirectional data; slew-rate controlled; ttl input; three-state output d10 11 i/o bit 10 of bidirectional data; slew-rate controlled; ttl input; three-state output d11 12 i/o bit 11 of bidirectional data; slew-rate controlled; ttl input; three-state output d12 13 i/o bit 12 of bidirectional data; slew-rate controlled; ttl input; three-state output d13 14 i/o bit 13 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 15 - digital ground d14 16 i/o bit 14 of bidirectional data; slew-rate controlled; ttl input; three-state output d15 17 i/o bit 15 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 18 - digital ground v hold1 19 - voltage holding pin 1; internally connected to the v reg(3v3) and v hold2 pins. when v cc is connected to 5 v, this pin will output 3.3 v, hence do not connect it to 5 v. when v cc is connected to 3.3 v, this pin can either be connected to 3.3 v or left unconnected. in all cases, decouple this pin to dgnd. n.c. 20 - no connection; leave this pin open cs_n 21 i chip select input rd_n 22 i read strobe input wr_n 23 i write strobe input v hold2 24 - voltage holding pin 2; internally connected to the v reg(3v3) and v hold1 pins. when v cc is connected to 5 v, this pin will output 3.3 v, hence do not connect it to 5 v. when v cc is connected to 3.3 v, this pin can either be connected to 3.3 v or left unconnected. in all cases, decouple this pin to dgnd. dreq 25 o hc dma request output (programmable polarity); signals to the dma controller that the isp1160 wants to start a dma transfer; see section 10.4.1 table 2: pin description lqfp64 continued symbol [1] pin type description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 6 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. n.c. 26 - no connection; leave this pin open dack_n 27 i hc dma acknowledge input; when not in use, this pin must be connected to v cc via an external 10 k w resistor test_high 28 - this pin must be connected to v cc via an external 10 k w resistor int 29 o hc interrupt output; programmable level, edge triggered and polarity; see section 10.4.1 n.c. 30 - no connection; leave this pin open n.c. 31 o no connection; leave this pin open reset_n 32 i reset input (schmitt trigger); a low level produces an asynchronous reset (internal pull-up resistor) ndp_sel 33 i indicates to the hc software the number of downstream ports (ndp) present: 0 select 1 downstream port 1 select 2 downstream ports only changes the value of the ndp ?eld in the hcrhdescriptora register; both ports will always be enabled; see section 10.3.1 (internal pull-up resistor) eot 34 i dma master device to inform the isp1160 of end of dma transfer; active level is programmable; when not in use, this pin must be connected to v cc via an external 10 k w resistor; see section 10.4.1 dgnd 35 - digital ground n.c. 36 - no connection; leave this pin open test_low 37 - this pin must be connected to dgnd via an external 10 k w resistor n.c. 38 - no connection; leave this pin open test_low 39 - this pin must be connected to dgnd via a 1 m w resistor h_wakeup 40 i hc wake-up input; generates a remote wake-up from the suspend state (active high); when not in use, this pin must be connected to dgnd via an external 10 k w resistor (internal pull-down resistor) n.c. 41 - no connection; leave this pin open h_suspend 42 o hc suspend state indicator output; active high xtal1 43 i crystal input; connected directly to a 6 mhz crystal; when this pin is connected to an external clock source, pin xtal2 must be left open xtal2 44 o crystal output; connected directly to a 6 mhz crystal; when pin xtal1 is connected to an external clock source, this pin must be left open dgnd 45 - digital ground h_psw1_n 46 o power switching control output for downstream port 1; open-drain output table 2: pin description lqfp64 continued symbol [1] pin type description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 7 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names ending with underscore n (for example, name_n) represent active low signals. h_psw2_n 47 o power switching control output for downstream port 2; open-drain output n.c. 48 - no connection; leave this pin open n.c. 49 - no connection; leave this pin open h_dm1 50 ai/o usb d - data line for hc downstream port 1 h_dp1 51 ai/o usb d + data line for hc downstream port 1 h_dm2 52 ai/o usb d - data line for hc downstream port 2; when not in use, this pin must be left open h_dp2 53 ai/o usb d + data line for hc downstream port 2; when not in use, this pin must be left open h_oc1_n 54 i overcurrent sensing input for hc downstream port 1 h_oc2_n 55 i overcurrent sensing input for hc downstream port 2 v cc 56 - digital power supply input (3.0 v to 3.6 v or 4.75 v to 5.25 v). this pin supplies the internal 3.3 v regulator input. when connected to 5 v, the internal regulator will output 3.3 v to pins v reg(3v3) , v hold1 and v hold2 . when connected to 3.3 v, it will bypass the internal regulator. agnd 57 - analog ground v reg(3v3) 58 - internal 3.3 v regulator output; when pin v cc is connected to 5 v, this pin outputs 3.3 v. when pin v cc is connected to 3.3 v, connect this pin to 3.3 v. a0 59 i address input; selects command (a0 = 1) or data (a0 = 0) low_pw 60 i if low-current consumption (range of m s) is needed during suspend, connect this pin to address a2; otherwise, connect to dgnd n.c. 61 - no connection; leave this pin open dgnd 62 - digital ground d0 63 i/o bit 0 of bidirectional data; slew-rate controlled; ttl input; three-state output d1 64 i/o bit 1 of bidirectional data; slew-rate controlled; ttl input; three-state output table 2: pin description lqfp64 continued symbol [1] pin type description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 8 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. functional description 7.1 pll clock multiplier a 6 mhz to 48 mhz clock multiplier phase-locked loop (pll) is integrated on-chip. this allows for the use of a low-cost 6 mhz crystal, which also minimizes emi. no external components are required for the operation of the pll. 7.2 bit clock recovery the bit clock recovery circuit recovers the clock from the incoming usb data stream by using a 4 times oversampling principle. it is able to track jitter and frequency drift as speci?ed in universal serial bus speci?cation rev. 2.0. 7.3 analog transceivers two sets of transceivers are embedded in the chip for downstream ports with usb connector type a. the integrated transceivers are compliant with the universal serial bus speci?cation rev. 2.0 . these transceivers interface directly with the usb connectors and cables through external termination resistors. 7.4 philips serial interface engine (sie) the philips sie implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel to serial conversion, bit (de)stuf?ng, crc checking and generation, packet identi?er (pid) veri?cation and generation, address recognition, and handshake evaluation and generation. 8. microprocessor bus interface 8.1 programmed i/o (pio) addressing mode a generic pio interface is de?ned for speed and ease-of-use. it also allows direct interfacing to most microcontrollers. to a microcontroller, the isp1160 appears as a memory device with a 16-bit data bus and uses the a0 address line to access internal control registers and fifo buffer ram. therefore, the isp1160 occupies only two i/o ports or two memory locations of a microprocessor. external microprocessors can read from or write to the isp1160s internal control registers and fifo buffer ram through the programmed i/o (pio) operating mode. figure 3 shows the programmed i/o interface between a microprocessor and the isp1160.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 9 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.2 dma mode the isp1160 also provides the dma mode for external microprocessors to access its internal fifo buffer ram. data can be transferred by the dma operation between a microprocessors system memory and the isp1160s internal fifo buffer ram. remark: the dma operation must be controlled by the external microprocessor systems dma controller (master). figure 4 shows the dma interface between a microprocessor system and the isp1160. the isp1160 provides a dma channel controlled by dreq for dack_n signals for the dma transfer between a microprocessors system memory and the isp1160 hcs internal fifo buffer ram. the eot signal is an external end-of-transfer signal used to terminate the dma transfer. some microprocessors may not have this signal. in this case, the isp1160 provides an internal eot signal to terminate the dma transfer as well. setting the hcdmacon?guration register (21h to read, a1h to write) enables the isp1160s hc internal dma counter for the dma transfer. when the dma counter reaches the value set in the hctransfercounter register (22h to read, a2h to write), an internal eot signal will be generated to terminate the dma transfer. fig 3. programmed i/o interface between a microprocessor and the isp1160. 004aaa061 d [ 15:0 ] rd_n wr_n cs_n a1 micro- processor isp1160 d [ 15:0 ] m p bus i/f rd_n wr_n cs_n a0 irq1 int fig 4. dma interface between a microprocessor and the isp1160. 004aaa062 d [ 15:0 ] rd_n wr_n dack1_n dreq1 eot micro- processor isp1160 d [ 15:0 ] m p bus i/f rd_n wr_n dack_n dreq eot
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 10 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.3 control registers access by pio mode 8.3.1 i/o port addressing ta b l e 3 shows the isp1160s i/o port addressing. complete decoding of the i/o port address should include the chip select signal cs_n and the address line a0. however, the direction of access of i/o ports is controlled by the rd_n and wr_n signals. when rd_n is low, the microprocessor reads data from the isp1160s data port. when wr_n is low, the microprocessor writes a command to the command port, or writes data to the data port. figure 5 illustrates how an external microprocessor accesses the isp1160s internal control registers. 8.3.2 register access phases the isp1160s register structure is a command-data register pair structure. a complete register access cycle comprises a command phase followed by a data phase. the command (also known as the index of a register) points the isp1160 to the next register to be accessed. a command is 8 bits long. on a microprocessors 16-bit data bus, a command occupies the lower byte, with the upper byte ?lled with zeros. figure 6 shows a complete 16-bit register access cycle for the isp1160. the microprocessor writes a command code to the command port, and then reads from or writes the data word to the data port. take the example of a microprocessor attempting to read the isp1160s id, which is saved in the hcs hcchipid register (index 27h, read only). the 16-bit register access cycle is therefore: 1. the microprocessor writes the command code of 27h (0027h in 16-bit width) to the hc command port 2. the microprocessor reads the data word of the chips id from the hc data port. table 3: i/o port addressing port cs_n a0 access data bus width (bits) description 0 0 0 r/w 16 hc data port 101w16 hc command port when a0 = 0, microprocessor accesses the data port. when a0 = 1, microprocessor accesses the command port. fig 5. access to internal control registers. 004aaa075 cmd/data switch commands control registers command register data port a0 command port . . . host bus i/f 1 0
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 11 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. most of the isp1160s internal control registers are 16-bit wide. some of the internal control registers, however, are 32-bit wide. figure 7 shows how the isp1160s 32-bit internal control register is accessed. the complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. in the two data phases, the microprocessor ?rst reads or writes the lower 16-bit data, followed by the upper 16-bit data. to further describe the complete access cycles of the internal control registers, the status of some pins of the microprocessor bus interface are shown in figure 8 . 8.4 fifo buffer ram access by pio mode since the isp1160s internal memory is structured as a fifo buffer ram, the fifo buffer ram is mapped to dedicated register ?elds. therefore, accessing the internal fifo buffer ram is similar to accessing the internal control registers in multiple data phases. fig 6. 16-bit register access cycle. fig 7. 32-bit register access cycle. fig 8. accessing hc control registers. mgt937 read/write data (16 bits) 16-bit register access cycle t write command (16 bits) mgt938 read/write data (lower 16 bits) 32-bit register access cycle t read/write data (upper 16 bits) write command (16 bits) signals valid status cs_n 0 a0 1 valid status 0 0 valid status 0 0 rd_n, wr_n rd_n = 1, wr_n = 0 rd_n = 0 (read) or wr_n = 0 (write) data bus command code register data (upper word) register data (lower word) rd_n = 0 (read) or wr_n = 0 (write) 004aaa370
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 12 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. figure 9 shows a complete access cycle of the hc internal fifo buffer ram. for a write cycle, the microprocessor ?rst writes the fifo buffer rams command code to the command port, and then writes the data words one by one to the data port until half of the transfers byte count is reached. the hctransfercounter register (22h to read, a2h to write) is used to specify the byte count of a fifo buffer rams read cycle or write cycle. every access cycle must be in the same access direction. the read cycle procedure is similar to the write cycle. 8.5 fifo buffer ram access by dma mode the dma interface between a microprocessor and the isp1160 is shown in figure 4 . when doing a dma transfer, at the beginning of every burst the isp1160 outputs a dma request to the microprocessor via pin dreq. after receiving this signal, the microprocessor will reply with a dma acknowledge to the isp1160 via pin dack_n, and at the same time, execute the dma transfer through the data bus. in the dma mode, the microprocessor must issue a read or write signal to the isp1160s pins rd_n or wr_n. the isp1160 will repeat the dma cycles until it receives an eot signal to terminate the dma transfer. the isp1160 supports both external and internal eot signals. the external eot signal is received as input on pin eot, and generally comes from the external microprocessor. the internal eot signal is generated inside the isp1160. to select either eot method, set the appropriate dma con?guration register (see section 10.4.2 ). for example, setting dmacounterselect (bit 2) of the hcdmacon?guration register (21h to read, a1h to write) to logic 1 will enable the dma counter for dma transfer. when the dma counter reaches the value of the hctransfercounter register, the internal eot signal will be generated to terminate the dma transfer. the isp1160 supports either single-cycle dma operation or burst mode dma operation; see figure 10 and figure 11 . fig 9. internal fifo buffer ram access cycle. mgt941 read/write data #1 (16 bits) fifo buffer ram access cycle (transfer counter = 2n) t read/write data #2 (16 bits) read/write data #n (16 bits) write command (16 bits)
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 13 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. in figure 10 and figure 11 , the dma transfer is con?gured such that dreq is active high and dack_n is active low. 8.6 interrupts the isp1160 has an interrupt request pin int. 8.6.1 pin con?guration the interrupt output signals have four con?guration modes: mode 0 mode 0 level trigger, active low mode 1 mode 1 level trigger, active high mode 2 mode 2 edge trigger, active low mode 3 mode 3 edge trigger, active high. n = 1/2 byte count of transfer data. fig 10. dma transfer in single-cycle mode. 004aaa368 dreq dack_n d [ 15:0 ] eot data #1 data #2 data #n rd_n or wr_n n = 1/2 byte count of transfer data, k = number of cycles/burst. fig 11. dma transfer in burst mode. 004aaa369 data #1 data #k data #2k data #n data #(k + 1) data #(n - k + 1) dreq dack_n d [ 15:0 ] eot rd_n or wr_n
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 14 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. figure 12 shows these four interrupt con?guration modes. they are programmable through the hchardware con?guration register (see section 10.4.1 ), which is also used to disable or enable the signals. 8.6.2 interrupt output pin (int) to program the four con?guration modes of the hcs interrupt output signal (int), set interruptpintrigger and interruptoutputpolarity (bits 1 and 2) of the hchardwarecon?guration register (20h to read, a0h to write). interruptpinenable (bit 0) is used as the master enable setting for pin int. int has many associated interrupt events as shown as in figure 13 . fig 12. interrupt pin operating modes. mgt944 int active int active clear or disable int mode 1 level triggered, active high int int 166 ns mode 2 edge triggered, active low int active int 166 ns mode 3 edge triggered, active high int active clear or disable int mode 0 level triggered, active low int
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 15 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. there are two groups of interrupts represented by group 1 and group 2 in figure 13 . a pair of registers control each group. group 2 contains six possible interrupt events (recorded in the hcinterruptstatus register). on occurrence of any of these events, the corresponding bit would be set to logic 1; and if the corresponding bit in the hcinterruptenable register is also logic 1, the 6-input or gate would output a logic 1. this output is and-ed with the value of mie (bit 31 of hcinterruptenable). logic 1 at the and gate will cause the opr bit in the hc m pinterrupt register to be set to logic 1. group 1 contains six possible interrupt events, one of which is the output of group 2 interrupt sources. the hc m pinterrupt and hc m pinterruptenable registers work in the same way as the hcinterruptstatus and hcinterruptenable registers in the interrupt group 2. the output from the 6-input or gate is connected to a latch, which is controlled by interruptpinenable (bit 0 of the hchardwarecon?guration register). in the event in which the software wishes to temporarily disable the interrupt output of the isp1160 host controller, the following procedure should be followed: 1. make sure that the interruptpinenable bit in the hchardwarecon?guration register is set to logic 1. 2. clear all bits in the hc m pinterrupt register. 3. set the interruptpinenable bit to logic 0. fig 13. hc interrupt logic. 004aaa102 sofitlint atlint alleotinterrupt opr_reg hcsuspended hcpinterrupt register hcinterruptenable register hcinterruptstatus register clkready rhsc fno ue rd sf so rhsc fno ue rd sf so mie or sofitlint atlint alleotinterrupt opr_reg hcsuspended hcpinterruptenable register clkready or latch int group 2 interruptpinenable hchardwareconfiguration register group 1 le
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 16 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. to re-enable the interrupt generation: 1. set all bits in the hc m pinterrupt register. 2. set the interruptpinenable bit to logic 1. remark: the interruptpinenable bit in the hchardwarecon?guration register latches the interrupt output. when this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operations on the interrupt control registers. if int1 is asserted, and the host controller driver (hcd) wishes to temporarily mask off the int signal without clearing the hc m pinterrupt register, the following procedure should be followed: 1. make sure that the interruptpinenable bit is set to logic 1. 2. clear all bits in the hc m pinterruptenable register. 3. set the interruptpinenable bit to logic 0. to re-enable the interrupt generation: 1. set all bits in the hc m pinterruptenable register according to the hcd requirements. 2. set the interruptpinenable bit to logic 1. 9. host controller (hc) 9.1 hcs four usb states the isp1160s usb hc has four usb statesusboperational, usbreset, usbsuspend and usbresumethat de?ne the hcs usb signalling and bus states responsibilities. the signals are visible to the host controller driver (hcd) via the isp1160 usb hcs control registers.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 17 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. the usb states are re?ected in the hostcontrollerfunctionalstate ?eld of the hccontrol register (01h to read, 81h to write), which is located at bits 7 and 6 of the register. the hcd can perform only the usb state transitions shown in figure 14 . remark: the software reset in figure 14 is not caused by the hcsoftwarereset command. it is caused by the hostcontrollerreset ?eld of the hccommandstatus register (02h to read, 82h to write). 9.2 generating usb traf?c usb traf?c can be generated only when the isp1160 usb hc is in the usboperational state. therefore, the hcd must set the hostcontrollerfunctionalstate ?eld of the hccontrol register before generating usb traf?c. a simplistic ?ow diagram showing when and how to generate usb traf?c is shown in figure 15 . for greater accuracy, refer to the universal serial bus speci?cation rev. 2.0 for the usb protocol and the isp1160 usb hcs register usage. fig 14. the isp1160 hcs usb states. mgt947 usboperational usbsuspend usbresume usbresume write or remote wake-up usbreset usboperational write usboperational write usbsuspend write usbreset write usbreset write usbreset write hardware or software reset
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 18 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. description of figure 15 : 1. reset this includes hardware reset by pin reset_n and software reset by the hcsoftwarereset command (a9h). the reset function will clear all the hcs internal control registers to their reset status. after reset, the hcd must initialize the isp1160 usb hc by setting some registers. 2. initialize hc it includes: a. setting the physical size for the hcs internal fifo buffer ram by setting the hcitlbufferlength register (2ah to read, aah to write) and the hcatlbufferlength register (2bh to read, abh to write). b. setting the hchardwarecon?guration register according to requirements. c. clearing interrupt events, if required. d. enabling interrupt events, if required. e. setting the hcfminterval register (0dh to read, 8dh to write). f. setting the hcs root hub registers. g. setting the hccontrol register to move the hc into the usboperational state. see also section 9.5 . 3. entry the normal entry point. the microprocessor returns to this point when there are hc requests. 4. need usb traf?c usb devices need the hc to generate usb traf?c when they have usb traf?c requests such as: a. connecting to or disconnecting from downstream ports b. issuing the resume signal to the hc. to generate usb traf?c, the hcd must enter the usb transaction loop. fig 15. isp1160 hc usb transaction loop. mgt948 need usb traffic? prepare ptd data in m p system ram initialize hc transfer ptd data into hc fifo buffer ram hc performs usb transactions via usb bus i/f hc informs hcd of usb traffic results hc interprets ptd data exit entry hc state = usboperational no yes reset
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 19 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. prepare ptd data in m p system ram the communication between the hcd and the isp1160 hc is in the form of philips transfer descriptor (ptd) data. the ptd data provides usb traf?c information about the commands, status and usb data packets. the physical storage media of ptd data for the hcd is the microprocessors system ram. for the isp1160s hc, the storage media is the internal fifo buffer ram. the hcd prepares ptd data in the microprocessors system ram for transfer to the isp1160s hc internal fifo buffer ram. 6. transfer ptd data into hcs fifo buffer ram when ptd data is ready in the microprocessors system ram, the hcd must transfer the ptd data from the microprocessors system ram into the isp1160s internal fifo buffer ram. 7. hc interprets ptd data the hc determines what usb transactions are required based on the ptd data that has been transferred into the internal fifo buffer ram. 8. hc performs usb transactions via usb bus interface the hc performs the usb transactions with the speci?ed usb device endpoint through the usb bus interface. 9. hc informs hcd of the usb traf?c results the usb transaction status and the feedback from the speci?ed usb device endpoint will be put back into the isp1160s hc internal fifo buffer ram in ptd data format. the hcd can read back the ptd data from the internal fifo buffer ram. 9.3 ptd data structure the philips transfer descriptor (ptd) data structure provides communication between the hcd and the isp1160s usb hc. the ptd data contains information required by the usb traf?c. ptd data consists of a ptd followed by its payload data, as shown in figure 16 . fig 16. ptd data in fifo buffer ram. mgt949 ptd fifo buffer ram payload data ptd data #1 ptd payload data payload data ptd ptd data #2 ptd data #n top bottom
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 20 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. the ptd data structure is used by the hc to de?ne a buffer of data that will be moved to or from an endpoint in the usb device. this data buffer is set up for the current frame (1 ms frame) by the hcd. the payload data for every transfer in the frame must have a ptd as the header to describe the characteristic of the transfer. the ptd data is dword (double-word or 4-byte) aligned. 9.3.1 ptd data header de?nition the ptd forms the header of the ptd data. it tells the hc the transfer type, where the payload data should go, and the actual size of the payload data. a ptd is an 8-byte data structure that is very important for hcd programming. table 4: philips transfer descriptor (ptd): bit allocation bit 7 6 5 4 3 2 1 0 byte 0 actualbytes[7:0] byte 1 completioncode[3:0] active toggle actualbytes[9:8] byte 2 maxpacketsize[7:0] byte 3 endpointnumber[3:0] last speed maxpacketsize[9:8] byte 4 totalbytes[7:0] byte 5 reserved b5_5 reserved directionpid[1:0] totalbytes[9:8] byte 6 format functionaddress[6:0] byte 7 reserved
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 21 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 5: philips transfer descriptor (ptd): bit description symbol access description actualbytes[9:0] r/w contains the number of bytes that were transferred for this ptd. completioncode[3:0] r/w 0000 noerror general td or isochronous data packet processing completed with no detected errors. 0001 crc last data packet from endpoint contained a crc error. 0010 bitstuf?ng last data packet from endpoint contained a bit stuf?ng violation. 0011 datatogglemismatch last packet from endpoint had data toggle pid that did not match the expected value. 0100 stall td was moved to the done queue because the endpoint returned a stall pid. 0101 devicenotresponding device did not respond to token (in) or did not provide a handshake (out). 0110 pidcheckfailure check bits on pid from endpoint failed on data pid (in) or handshake (out). 0111 unexpectedpid received pid was not valid when encountered or pid value is not de?ned. 1000 dataoverrun the amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in the maximumpacketsize ?eld of endpoint descriptor) or the remaining buffer size. 1001 dataunderrun the endpoint returned is less than maximumpacketsize and that amount was not suf?cient to ?ll the speci?ed buffer. 1010 reserved - 1011 reserved - 1100 bufferoverrun during an in, the hc received data from an endpoint faster than it could be written to system memory. 1101 bufferunderrun during an out, the hc could not retrieve data from the system memory fast enough to keep up with the usb data rate. active r/w set to logic 1 by ?rmware to enable the execution of transactions by the hc. when the transaction associated with this descriptor is completed, the hc sets this bit to logic 0, indicating that a transaction for this element will not be executed when it is next encountered in the schedule. toggle r/w used to generate or compare the data pid value (data0 or data1). it is updated after each successful transmission or reception of a data packet. maxpacketsize[9:0] r the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. endpointnumber[3:0] r usb address of the endpoint within the function. last r last ptd of a list (itl or atl). logic 1 indicates that the ptd is the last ptd. speed r speed of the endpoint: 0 full speed 1 low speed totalbytes[9:0] r speci?es the total number of bytes to be transferred with this data structure. for bulk and control only, this can be greater than maximumpacketsize.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 22 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4 hcs internal fifo buffer ram structure 9.4.1 partitions according to the universal serial bus speci?cation rev. 2.0 , there are four types of usb data transfers: control, bulk, interrupt and isochronous. the hcs internal fifo buffer ram has a physical size of 4 kbytes. this internal fifo buffer ram is used for transferring data between the microprocessor and usb peripheral devices. this on-chip buffer ram can be partitioned into two areas: acknowledged transfer list (atl) buffer and isochronous (iso) transfer list (itl) buffer. the itl buffer is a ping-pong structured fifo buffer ram that is used to keep the payload data and their ptd header for isochronous transfers. the atl buffer is a non ping-pong structured fifo buffer ram that is used for the other three types of transfers. the itl buffer can be further partitioned into itl0 and itl1 for the ping-pong structure. the itl0 and itl1 buffers always have the same size. the microprocessor can put iso data into either the itl0 buffer or the itl1 buffer. when the microprocessor accesses an itl buffer, the hc can take over the other itl buffer at the same time. this architecture improves the iso transfer performance. the hcd can assign the logical size for the atl buffer and itl buffers at any time, but normally at initialization after power-on reset. this is done by setting the hcatlbufferlength register (2bh to read, abh to write) and the hcitlbufferlength register (2ah to read, aah to write), respectively. the total length (atl buffer + itl buffer) should not exceed the maximum ram size of 4 kbytes. figure 17 shows the partitions of the internal fifo buffer ram. when assigning buffer ram sizes, follow this formula: atl buffer length + 2 (itl buffer size) 1000h (that is, 4 kbytes) where: itl buffer size = itl0 buffer length = itl1 buffer length the following assignments are examples of legal uses of the internal fifo buffer ram: ? atl buffer length = 800h, itl buffer length = 400h. this is the maximum use of the internal fifo buffer ram. directionpid[1:0] r 00 setup 01 out 10 in 11 reserved b5_5 r/w this bit is logic 0 at power-on reset. when this feature is not used, software used for the isp1160 is the same for the isp1161 and the isp1161a. when this bit is set to logic 1 in this ptd for interrupt endpoint transfer, only one ptd usb transaction will be sent out in 1ms. format r the format of this data structure. if this is a control, bulk or interrupt endpoint, then format = 0. if this is an isochronous endpoint, then format = 1. functionaddress[6:0] r this is the usb address of the function containing the endpoint that this ptd refers to. table 5: philips transfer descriptor (ptd): bit description continued symbol access description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 23 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? atl buffer length = 400h, itl buffer length = 200h. this is insuf?cient use of the internal fifo buffer ram. ? atl buffer length = 1000h, itl buffer length = 0h. this will use the internal fifo buffer ram for only atl transfers. the actual requirement for the buffer ram needs to reach not the maximum size. you can make your selection based on your application. the following are some calculations of the iso_a or iso_b space for a frame of data: ? maximum number of useful data sent during one usb frame is 1280 bytes (20 iso packets of 64 bytes). the total ram size needed is: 20 8 + 1280 = 1440 bytes. ? maximum number of packets for different endpoints sent during one usb frame is 150 (150 iso packets of 1 byte). the total ram size needed is: 150 8 + 150 1 = 1350 bytes. ? the ping buffer ram (itl0) and the pong buffer ram (itl1) have a maximum size of 2 kbytes each. all data needed for one frame can be stored in the ping or the pong buffer ram. when the embedded system wants to initiate a transfer to the usb bus, the data needed for one frame is transferred to the atl buffer or the itl buffer. the microprocessor detects the buffer status through interrupt routines. when the hcbufferstatus register (2ch to read only) indicates that the buffer is empty, then the microprocessor writes data into the buffer. when the hcbufferstatus register indicates that the buffer is full, the data is ready on the buffer, and the microprocessor needs to read data from the buffer. for every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. however, each of the interrupt types de?ned in this speci?cation can be enabled or disabled by setting hc m pinterruptenable register bits accordingly. fig 17. hc internal fifo buffer ram partitions. mgt950 not used atl buffer itl0 top bottom itl1 iso_a fifo buffer ram iso_b control/bulk/interrupt data programmable sizes 4 kbytes itl buffer atl
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 24 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. the data transfer can be done via the pio mode or the dma mode. the data transfer rate can go up to 15 mbyte/s. in the dma operation, the single-cycle or multi-cycle burst modes are supported. multi-cycle burst modes of 1, 4 or 8 cycles per burst are supported for the isp1160. 9.4.2 data organization ptd data is used for every data transfer between a microprocessor and the usb bus, and the ptd data resides in the buffer ram. for an out or setup transfer, the payload data is placed just after the ptd, after which the next ptd is placed. for an in transfer, ram space is reserved for receiving a number of bytes that is equal to the total bytes of the transfer. after this, the next ptd and its payload data are placed (see figure 18 ). remark: the ptd is de?ned for both the atl and itl type data transfer. for itl, the ptd data is put into itl buffer ram, and the isp1160 takes care of the ping-pong action for the itl buffer ram access. the ptd data (ptd header and its payload data) is a structure of dword alignment. this means that the memory address is organized in blocks of 4 bytes. therefore, the ?rst byte of every ptd and the ?rst byte of every payload data are located at an address that is a multiple of 4. figure 19 illustrates an example in which the ?rst payload data is 14 bytes long, meaning that the last byte of the payload data is at the location 15h. the next addresses (16h and 17h) are not multiples of 4. therefore, the ?rst byte of the next ptd will be located at the next multiple-of-four address (18h). fig 18. buffer ram data organization. mgt952 ptd of out transfer ram buffer payload data of out transfer ptd of in transfer empty space for in total data ptd of out transfer payload data of out transfer top bottom 000h 7ffh
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 25 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.3 operation and c program example figure 20 shows the block diagram for internal fifo buffer ram operations in the pio mode. the isp1160 provides one register as the access port for each buffer ram. for the itl buffer ram, the access port is the itlbufferport register (40h to read, c0h to write). for the atl buffer ram, the access port is the atlbufferport register (41h to read, c1h to write). the buffer ram is an array of bytes (8 bits) while the access port is a 16-bit register. therefore, each read/write operation on the port accesses two consecutive memory locations, incrementing the pointer of the internal buffer ram by two. the lower byte of the access port register corresponds to the data byte at the even location of the buffer ram, and the upper byte corresponds to the next data byte at the odd location of the buffer ram. regardless of the number of data bytes to be transferred, the command code must be issued merely once, and it will be followed by a number of accesses of the data port (see section 8.4 ). when the pointer of the buffer ram reaches the value of the hctransfercounter register, an internal eot signal will be generated to set bit 2, alleotinterrupt, of the hc m pinterrupt register and update the hcbufferstatus register, to indicate that the whole data transfer has been completed. for itl buffer ram, every start of frame (sof) signal (1 ms) will cause toggling between itl0 and itl1 but this depends on the buffer status. if both itl0bufferfull and itl1bufferfull of the hcbufferstatus register are already logic 1, meaning that both itl0 and itl1 buffer rams are full, the toggling will not happen. in this case, the microprocessor will always have access to itl1. fig 19. ptd data with dword alignment in buffer ram. mgt953 payload data (14 bytes) ptd (8 bytes) ptd (8 bytes) 00h top 08h 15h 18h 20h payload data ram buffer
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 26 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. following is an example of a c program that shows how to write data into the atl buffer ram. the total number of data bytes to be transferred is 80 (decimal) that will be set into the hctransfercounter register as 50h. the data consists of four types of ptd data: 1. the ?rst ptd header (in) is 8 bytes, followed by 16 bytes of space reserved for its payload data; 2. the second ptd header (in) is also 8 bytes, followed by 8 bytes of space reserved for its payload data; 3. the third ptd header (out) is 8 bytes, followed by 16 bytes of payload data with values beginning from 0h to fh incrementing by 1; 4. the fourth ptd header (out) is also 8 bytes, followed by 8 bytes of payload data with values beginning from 0h to eh incrementing by 2. in all ptds, we have assigned device address as 5 and endpoint 1. actualbytes is always zero (0). totalbytes equals the number of payload data bytes transferred. however, note that for bulk and control transfers, totalbytes can be greater than maxpacketsize. ta b l e 6 shows the results after running this program. fig 20. pio access to internal fifo buffer ram. mgt951 commands pointer automatically increments by 2 transfercounter bufferstatus bufferstatus internal eot itlbufferport atlbufferport atl buffer ram (8-bit width) control registers command register data port t eot 1 2 = 0 toggle command port m pinterrupt 22h/a2h 2ch 40h/c0h 41h/c1h 24h/a4h 000h 7ffh 001h itl1 buffer ram (8-bit width) 000h 3ffh 001h itl0 buffer ram (8-bit width) 000h 3ffh 001h a0 host bus i/f 1 0 (16-bit width) sof
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 27 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. however, if communication with a peripheral usb device is desired, the device should be connected to the downstream port and pass enumeration. //the example program for writing atl buffer ram #include #include #include //define register commands #define whctransfercounter 0x22 #define whcupinterrupt 0x24 #define whcatlbufferlength 0x2b #define whcbufferstatus 0x2c // define i/o port address for hc #define hcdataport 0x290 #define hccmdport 0x292 //declare external functions to be used unsigned int hcregread(unsigned int windex); void hcregwrite(unsigned int windex,unsigned int wvalue); void main(void) { unsigned int i; unsigned int wcount,wdata; // prepare ptd data to be written into hc atl buffer ram: unsigned int ptddata[0x28] = { 0x0800,0x1010,0x0810,0x0005, //ptd header for in token #1 //reserved space for payload data of in token #1 0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1008,0x0808,0x0005, //ptd header for in token #2 //reserved space for payload data of in token #2 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1010,0x0410,0x0005, //ptd header for out token #1 0x0100,0x0302,0x0504,0x0706, //payload data for out token #1 0x0908,0x0b0a,0x0d0c,0x0f0e, 0x0800,0x1808,0x0408,0x0005, //ptd header for out token #2 0x0200,0x0604,0x0a08,0x0e0c //payload data for out token #2 }; hcregwrite(whcupinterrupt,0x04); //clear eot interrupt bit //hcregwrite(whcitlbufferlength,0x0); hcregwrite(whcatlbufferlength,0x1000); //ram full use for atl //set the number of bytes to be transferred hcregwrite(whctransfercounter,0x50); wcount = 0x28; //get word count outport (hccmdport,0x00c1); //command for atl buffer write
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 28 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. //write 80 (0x50) bytes of data into atl buffer ram for (i = 0;i philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 29 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. the end of the frame for full-speed and low-speed packets. by programming these ?elds, the effective usb bus usage can be changed. furthermore, the size of the itl buffers (hcitlbufferlength, 2ah to read, aah to write) is programmed. if a usb frame contains both iso and at packets, two interrupts will be generated per frame. one interrupt is issued concurrently with the sof. this interrupt (itlint is set in the hc m pinterrupt register) triggers reading and writing of the itl buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. next the programmable atl interrupt (bit atlint is set in the hc m pinterrupt register) is issued, which triggers reading and writing of the atl buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. if the microprocessor cannot handle the iso interrupt before the next iso interrupt, disrupted iso traf?c can result. to be able to send more than one packet to the same control or bulk endpoint in the same frame, the active bit and the totalbytes ?eld are introduced (see ta b l e 5 ). bit active is cleared only if all data of the philips transfer descriptor (ptd) have been transferred or if a transaction at that endpoint contained a fatal error. if all ptds of the atl are serviced once and the frame is not over yet, the hc starts looking for a ptd with bit active still set. if such a ptd is found and there is still enough time in this frame, another transaction is started on the usb bus for this endpoint. for iso processing, the hcd also has to take care of the bufferstatus register (2ch, read only) for the itl buffer ram operations. after the hcd writes iso data into itl buffer ram, the itl0bufferfull or itl1bufferfull bit (depending on whether it is itl0 or itl1) will be set to logic 1. after the hc processes the iso data in the itl buffer ram, the corresponding itl0bufferdone or itl1bufferdone bit will automatically be set to logic 1. the hcd can clear the buffer status bits by a read of the itl buffer ram. this must be done within the 1 ms frame from which itl0bufferdone or itl1bufferdone was set. failure to do so will cause the iso processing to stop and a power-on reset or software reset will have to be applied to the hc, a usb reset to the usb bus must not be made. for example, the hcd writes iso_a data into the itl0 buffer in the ?rst frame. this will cause the hcbufferstatus register to show that the itl0 buffer is full by setting bit itl0bufferfull to logic 1. at this stage, the hcd cannot write iso data into the itl0 buffer ram again. in the second frame, the hc will process the iso_a data in the itl0 buffer. at the same time, the hcd can write iso_b data into the itl1 buffer. when the next sof comes (the beginning of the third frame), both itl1bufferfull and itl0bufferdone are automatically set to logic 1. in the third frame, the hcd has to read at least two bytes (one word) of the itl0 buffer to clear both the itl0bufferfull and itl0bufferdone bits. if both are not cleared, when the next sof comes (the beginning of the fourth frame) the
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 30 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. itl0bufferdone and itl0bufferfull bits will be cleared automatically. this also applies to the itl1 buffer because itl0 and itl1 are ping-pong structured buffers. to recover from this state, a power-on reset or software reset will have to be applied. 9.5.1 time domain behavior in example 1 ( figure 21 ), the cpu is fast enough to read back and download a scenario before the next interrupt. note that on the iso interrupt of frame n: ? the iso packet for frame n + 1 will be written ? the at packet for frame n + 1 will be written. in example 2 ( figure 22 ), the microprocessor is still busy transferring the at data when the iso interrupt of the next frame (n + 1) is raised. as a result, there will be no at traf?c in frame n + 1. the hc does not raise an at interrupt in frame n + 1. the at part is simply postponed until frame n + 2. on the at n + 2 interrupt, the transfer mechanism is back to the normal operation. this simple mechanism ensures, among other things, that control transfers are not dropped systematically from the usb in case of an overloaded microprocessor. in example 3 ( figure 23 ), the iso part is still being written while the start of frame (sof) of the next frame has occurred. this will result in unde?ned behavior for the iso data on the usb bus in frame n + 1 (depending on whether the exact timing data is corrupted or not). the hc should not raise an at interrupt in frame n + 1. fig 21. hc time domain behavior: example 1. mgt954 (frame n) (frame n + 1) (frame n + 2) (frame n + 3) read iso_a(n - 1) write iso_a(n + 1) sof read at(n) write at(n + 1) at interrupt traffic on usb iso interrupt fig 22. hc time domain behavior: example 2. mgt955 (frame n) (frame n + 1) (frame n + 2) (frame n + 3)
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 31 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.2 control transaction limitations the different phases of a control transfer (setup, data and status) should never be put in the same atl. 9.6 microprocessor loading the maximum amount of data that can be transferred for an endpoint in one frame is 1023 bytes. the number of usb packets that are needed for this batch of data depends on the maximum packet size that is speci?ed. the hcd has to schedule the transactions in a frame. on the other hand, the microprocessor must have the ability to handle the interrupts coming from the hc every 1 ms. it must also be able to do the scheduling for the next frame, reading the frame information from and writing the next frame information to the buffer ram in the time between the end of the current frame and the start of the next frame. 9.7 internal pull-down resistors for downstream ports there are four internal 15 k w pull-down resistors built in the isp1160 for the two downstream ports: two resistors for each port. these resistors are software selectable by programming bit 12 (2_downstreamport15kresistorsel) of the hchardwarecon?guration register (20h to read, a0h to write). when bit 12 is logic 0, external 15 k w pull-down resistors are used. when bit 12 is logic 1, internal 15 k w pull-down resistors are used. see figure 24 . this feature is a cost-saving option. however, the power-on reset default value of bit 12 is logic 0. if using the internal resistors, the hcd must check this bit status after every reset, because a reset action (hardware or software) will clear this bit. fig 23. hc time domain behavior: example 3. mgt956 (frame n) (frame n + 1) (frame n + 2) (frame n + 3)
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 32 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.8 overcurrent detection and power switching control a downstream port provides 5 v power supply to v bus . the isp1160 has built-in hardware functions to monitor the downstream ports loading conditions and control their power switching. these hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. h_psw1_n and h_psw2_n are power switching control output pins (active low, open-drain) for downstream ports 1 and 2, respectively. h_oc1_n and h_oc2_n are overcurrent detection input pins for downstream ports 1 and 2, respectively. figure 25 shows the isp1160 downstream port power management scheme. using either internal or external 15 k w resistors. fig 24. use of 15 k w pull-down resistors on downstream ports. 004aaa064 22 w 22 w bit 12 hchardware configuration isp1160 usb connector d - d + v bus internal 15 k w (2 ) external 15 k w (2 ) 47 pf (2 ) n represents the downstream port numbers (n = 1 or 2). fig 25. downstream port power management scheme. 004aaa065 1 3 0 reg bit 10 psw oc select oc detect regulator h_ocn_n h_pswn_n hc core c/l isp1160 v cc ( + 5 v or + 3.3 v) hchardware configuration
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 33 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.8.1 using an internal oc detection circuit the internal oc detection circuit can be used only when v cc (pin 56) is connected to a 5 v power supply. the hcd must set analogocenable, bit 10 of the hchardwarecon?guration register, to logic 1. an application using the internal oc detection circuit and internal 15 k w pull-down resistors is shown in figure 26 . in this example, the hcd must set both analogocenable and downstreamport15kresistorsel to logic 1. they are bit 10 and bit 12 of the hchardwarecon?guration register, respectively. when h_ocn_n detects an overcurrent status on a downstream port, h_pswn_n will output high, a logic 1 to turn off the 5 v power supply to the downstream port v bus . when there is no such detection, h_pswn_n will output low, a logic 0 to turn on the 5 v power supply to the downstream port v bus . in general applications, a p-channel mosfet can be used as the power switch for v bus . connect the 5 v power supply to the source of the p-channel mosfet, v bus to the drain, and h_pswn_n to the gate. call the voltage drop across the drain and source, the overcurrent detection voltage (v oc ). for the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold ( d v trip ) of 75 mv. when v oc exceeds v trip , h_pswn_n will output a high level, logic 1 to turn off the p-channel mosfet. if the p-channel mosfet has a r dson of 150 m w , the overcurrent threshold will be 500 ma. the selection of a p-channel mosfet with a different r dson will result in a different overcurrent threshold. n represents the downstream port number ( n=1or2). fig 26. using an internal oc detection circuit. 004aaa066 atx 1 3 0 reg psw oc select oc detect regulator v cc h_ocn_n v oc = + 5 v - v bus h_pswn_n h_dmn h_dpn hc core c/l sie usb downstream port connector 15 k w (2 ) 47 pf (2 ) 22 w 22 w isp1160 v bus + 5 v p-channel mosfet bit 10 bit 12 hchardware configuration hchardware configuration
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 34 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.8.2 using an external oc detection circuit when v cc (pin 56) is connected to a 3.3 v instead of the 5 v power supply, the internal oc detection circuit cannot be used. an external oc detection circuit must be used instead. regardless of the v cc value, an external oc detection circuit can always be used. to use an external oc detection circuit, analogocenable, bit 10 of the hchardwarecon?guration register, should be logic 0. by default after reset, this bit is already logic 0; therefore, the hcd does not need to clear this bit. figure 27 shows how to use an external oc detection circuit. 9.9 suspend and wake-up 9.9.1 hc suspended state the hc can be put into suspended state by setting the hccontrol register (01h to read, 81h to write). see figure 14 for the hcs ?ow of usb state changes. n represents the downstream port number ( n=1or2). fig 27. using an external oc detection circuit. v o v i oc en v cc h_ocn_n h_pswn_n h_dmn h_dpn usb downstream port connector 47 pf (2 ) 22 w 22 w v bus + 3.3 v or + 5 v + 5 v external oc detect 004aaa067 atx 1 3 0 reg psw oc select oc detect regulator hc core c/l sie 15 k w (2 ) isp1160 bit 10 bit 12 hchardware configuration hchardware configuration
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 35 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. in the suspended state, the device will consume considerably less power by turning off the internal 48 mhz clock, pll and crystal, and setting the internal regulator to power-down mode. the isp1160 suspend and resume clock scheme is shown in figure 28 . pin h_suspend is the sensing output pin for the hcs suspended state. when the hc goes into the usbsuspend state, this pin will output a high level (logic 1). this pin is cleared to low (logic 0) level only when the hc is put into a usbreset state or usboperational state (refer to the hccontrol register bits 7 to 6; 01h to read, 81h to write). bit 11, suspendclknotstop, of the hchardwarecon?guration register (20h to read, a0h to write), de?nes if the hc internal clock is stopped or kept running when the hc goes into the usbsuspend state. after the hc enters the usbsuspend state for 1.3 ms, the internal clock will be stopped if bit suspendclknotstop is logic 0. for details on power consumption, refer to philips application note an10022 isp1160x low power consumption . 9.9.2 hc wake-up from suspended state there are three methods to wake up the hc from the usbsuspend state: hardware wake-up, software wake-up, and usb bus resume. they are described as follows. wake-up by pin h_wakeup: pins h_suspend and h_wakeup provide hardware wake-up, a way of remote wake-up control for the hc without the need to access the hc internal registers. h_wakeup is an external wake-up control input pin for the hc. after the hc goes into the usbsuspend state, it can be woken up by sending a high level pulse to pin h_wakeup. this will turn on the hcs internal clock, and set bit 6, clkready, of the hc m pinterrupt register (24h to read, a4h to write). under the usbsuspend state, once pin h_wakeup goes high, after 160 m s, the internal clock will be up. if pin h_wakeup continues to be high, then the internal clock will be kept running, and the microprocessor can set the hc into usboperational state during this time. if h_wakeup goes low for more than 1.14 ms, the internal clock stops and the hc goes back into the usbsuspend state. fig 28. isp1160 suspend and resume clock scheme. 004aaa375 on on xosc_6mhz xosc on voltage regulator hc pll hc_clkok hc_rawclk48m hc_enableclock h_wakeup (pin) cs_n (pin) hc_needclock pll_lock pll_clkout on digital clock switch hc core hc_clk48mout hchardware configuration bit 11 (suspendclknotstop)
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 36 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. wake-up by pin cs_n (software wake-up): during the usbsuspend state, an external microprocessor issues a chip select signal through pin cs_n to the isp1160. this method of access to the isp1160 internal registers is a software wake-up. wake-up by usb devices: for the usb bus resume, a usb device attached to the root hub port issues a resume signal to the hc through the usb bus, switching the hc from the usbsuspend state to the usbresume state. this will also set bit resumedetected of the hcinterruptstatus register (03h to read, 83h to write). no matter which method is used to wake up the hc from the usbsuspend state, the corresponding interrupt bits must be enabled before the hc goes into the usbsuspend state so that the microprocessor can receive the correct interrupt request to wake up the hc. 10. hc registers the hc contains a set of on-chip control registers. these registers can be read or written by the host controller driver (hcd). the control and status register sets, frame counter register sets, and root hub register sets are grouped under the category of hc operational registers (32 bits). these operational registers are made compatible to openhci (host controller interface) operational registers. this allows the openhci hcd to be easily ported to the isp1160. reserved bits may be de?ned in future releases of this speci?cation. to ensure interoperability, the hcd must not assume that a reserved ?eld contains logic 0. furthermore, the hcd must always preserve the values of the reserved ?eld. when a r/w register is modi?ed, the hcd must ?rst read the register, modify the bits desired, and then write the register with the reserved bits still containing the original value. alternatively, the hcd can maintain an in-memory copy of previously written values that can be modi?ed and then written to the hc register. when a write to set or clear the register is performed, bits written to reserved ?elds must be logic 0. as shown in ta b l e 7 , the addresses (the commands for reading registers) of these 32-bit operational registers are similar to the offsets de?ned in the ohci speci?cation with the addresses being equal to offset divided by 4. table 7: hc registers summary address (hex) register width reference functionality read write 00 n/a hcrevision 32 section 10.1.1 on page 37 hc control and status registers 01 81 hccontrol 32 section 10.1.2 on page 38 02 82 hccommandstatus 32 section 10.1.3 on page 39 03 83 hcinterruptstatus 32 section 10.1.4 on page 40 04 84 hcinterruptenable 32 section 10.1.5 on page 42 05 85 hcinterruptdisable 32 section 10.1.6 on page 43 0d 8d hcfminterval 32 section 10.2.1 on page 44 hc frame counter registers 0e n/a hcfmremaining 32 section 10.2.2 on page 45 0f n/a hcfmnumber 32 section 10.2.3 on page 46 11 91 hclsthreshold 32 section 10.2.4 on page 47
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 37 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1 hc control and status registers 10.1.1 hcrevision register (r: 00h) code (hex): 00 read only 12 92 hcrhdescriptora 32 section 10.3.1 on page 48 hc root hub registers 13 93 hcrhdescriptorb 32 section 10.3.2 on page 50 14 94 hcrhstatus 32 section 10.3.3 on page 51 15 95 hcrhportstatus[1] 32 section 10.3.4 on page 53 16 96 hcrhportstatus[2] 32 section 10.3.4 on page 53 20 a0 hchardwarecon?guration 16 section 10.4.1 on page 57 hc dma and interrupt control registers 21 a1 hcdmacon?guration 16 section 10.4.2 on page 58 22 a2 hctransfercounter 16 section 10.4.3 on page 59 24 a4 hc m pinterrupt 16 section 10.4.4 on page 59 25 a5 hc m pinterruptenable 16 section 10.4.5 on page 61 27 n/a hcchipid 16 section 10.5.1 on page 62 hc miscellaneous registers 28 a8 hcscratch 16 section 10.5.2 on page 63 n/a a9 hcsoftwarereset 16 section 10.5.3 on page 63 2a aa hcitlbufferlength 16 section 10.6.1 on page 64 hc buffer ram control registers 2b ab hcatlbufferlength 16 section 10.6.2 on page 64 2c n/a hcbufferstatus 16 section 10.6.3 on page 65 2d n/a hcreadbackitl0length 16 section 10.6.4 on page 65 2e n/a hcreadbackitl1length 16 section 10.6.5 on page 66 40 c0 hcitlbufferport 16 section 10.6.6 on page 66 41 c1 hcatlbufferport 16 section 10.6.7 on page 67 table 7: hc registers summary continued address (hex) register width reference functionality read write table 8: hcrevision register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access rrrrrrrr
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 38 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.2 hccontrol register (r/w: 01h/81h) the hccontrol register de?nes the operating modes of the hc. remotewakeupenable (rwe) is modi?ed only by the hcd. code (hex): 01 read code (hex): 81 write bit 7 6 5 4 3 2 1 0 symbol rev[7:0] reset 00010000 access rrrrrrrr table 9: hcrevision register: bit description bit symbol description 31 to 8 - reserved 7 to 0 rev[7:0] revision: this read-only ?eld contains the bcd representation of the version of the hci speci?cation that is implemented by this hc. all hc implementations that are compliant with this speci?cation will have a value of 10h. table 10: hccontrol register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved rwe rwc reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol hcfs[1:0] reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 39 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.3 hccommandstatus register (r/w: 02h/82h) the hccommandstatus register is used by the hc to receive commands issued by the hcd, and it also re?ects the hcs current status. to the hcd, it appears to be a write to set register. the hc must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. the hcd may issue multiple distinct commands to the hc without concern for corrupting previously issued commands. the hcd has normal read access to all bits. the schedulingoverruncount ?eld indicates the number of frames with which the hc has detected the scheduling overrun error. this occurs when the periodic list does not complete before eof. when a scheduling overrun error is detected, the hc increments the counter and sets the schedulingoverrun ?eld in the hcinterruptstatus register. code (hex): 02 read table 11: hccontrol register: bit description bit symbol description 31 to 11 - reserved 10 rwe remotewakeupenable: this bit is used by the hcd to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. when this bit is set and the resumedetected bit in hcinterruptstatus is set, a remote wake-up is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9rwc remotewakeupconnected: this bit indicates whether the hc supports remote wake-up signaling. if remote wake-up is supported and used by the system, it is the responsibility of system ?rmware to set this bit during post. the hc clears the bit upon a hardware reset but does not alter it upon a software reset. remote wake-up signaling of the host system is host-bus-speci?c and is not described in this speci?cation. 8 - reserved 7 to 6 hcfs hostcontrollerfunctionalstate for usb: 00b usbreset 01b usbresume 10b usboperational 11b usbsuspend a transition to usboperational from another state causes start-of-frame (sof) generation to begin 1 ms later. the hcd may determine whether the hc has begun sending sofs by reading the startofframe ?eld of hcinterruptstatus. this ?eld can be changed by the hc only when in the usbsuspend state. the hc can move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the hc enters usbreset after a software reset and a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 to 0 - reserved
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 40 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): 82 write 10.1.4 hcinterruptstatus register (r/w: 03h/83h) this register provides the status of the events that cause hardware interrupts. when an event occurs, the hc sets the corresponding bit in this register. when a bit is set, a hardware interrupt is generated if the interrupt is enabled in the hcinterruptenable register (see section 10.1.5 ) and bit masterinterruptenable is set. the hcd can clear individual bits in this register by writing logic 1 to the bit positions to be cleared, but cannot set any of these bits. conversely, the hc can set bits in this register, but cannot clear these bits. table 12: hccommandstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved soc[1:0] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved hcr reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 13: hccommandstatus register: bit description bit symbol description 31 to 18 - reserved 17 to 16 soc[1:0] schedulingoverruncount: the ?eld is incremented on each scheduling overrun error. it is initialized to 00b and wraps around at 11b. it will be incremented when a scheduling overrun is detected even if schedulingoverrun in hcinterruptstatus has already been set. this is used by hcd to monitor any persistent scheduling problems. 15 to 1 - reserved 0 hcr hostcontrollerreset: this bit is set by the hcd to initiate a software reset of the hc. regardless of the functional state of the hc, it moves to the usbsuspend state in which most of the operational registers are reset, except those stated otherwise, and no host bus accesses are allowed. this bit is cleared by the hc upon the completion of the reset operation. the reset operation must be completed within 10 m s. this bit, when set, does not cause a reset to the root hub and no subsequent reset signaling should be asserted to its downstream ports.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 41 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): 03 read code (hex): 83 write table 14: hcinteruptstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 15: hcinterruptstatus register: bit description bit symbol description 31 to 7 - reserved 6 rhsc roothubstatuschange: this bit is set when the content of hcrhstatus or the content of any of hcrhportstatus[1:2] has changed. 5 fno framenumberover?ow: this bit is set when the msb of hcfmnumber (bit 15) changes value. 4ue unrecoverableerror: this bit is set when the hc detects a system error not related to usb. the hc does not proceed with any processing nor signaling before the system error has been corrected. the hcd clears this bit after the hc has been reset. ohci: always set to logic 0. 3rd resumedetected: this bit is set when the hc detects that a device on the usb is asserting resume signaling from a state of no resume signaling. this bit is not set when hcd enters the usbresume state. 2sf startofframe: at the start of each frame, this bit is set by the hc and an sof generated. 1 - reserved 0so schedulingoverrun: this bit is set when usb schedules for current frame overruns. a scheduling overrun will also cause the schedulingoverruncount of hccommandstatus to be incremented.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 42 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.5 hcinterruptenable register (r/w: 04h/84h) each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events generate a hardware interrupt. a hardware interrupt is requested on the host bus when three conditions occur: ? a bit is set in the hcinterruptstatus register ? the corresponding bit in the hcinterruptenable register is set ? bit masterinterruptenable is set. writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a logic 0 to a bit in this register leaves the corresponding bit unchanged. on a read, the current value of this register is returned. code (hex): 04 read code (hex): 84 write table 16: hcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 43 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.6 hcinterruptdisable register (r/w: 05h/85h) each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. thus, writing a logic 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing a logic 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on a read, the current value of the hcinterruptenable register is returned. code (hex): 05 read code (hex): 85 write table 17: hcinterruptenable register: bit description bit symbol description 31 mie masterinterruptenable by the hcd: a logic 0 is ignored by the hc. a logic 1 enables interrupt generation by events speci?ed in other bits of this register. 30 to 7 - reserved 6 rhsc 0 ignore 1 enable interrupt generation due to root hub status change 5 fno 0 ignore 1 enable interrupt generation due to frame number over?ow 4ue 0 ignore 1 enable interrupt generation due to unrecoverable error 3rd 0 ignore 1 enable interrupt generation due to resume detect 2sf 0 ignore 1 enable interrupt generation due to start of frame 1 - reserved 0so 0 ignore 1 enable interrupt generation due to scheduling overrun table 18: hcinterruptdisable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 44 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2 hc frame counter registers 10.2.1 hcfminterval register (r/w: 0dh/8dh) the hcfminterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive sofs), and a 15-bit value indicating the full-speed maximum packet size that the hc may transmit or receive without causing a scheduling overrun. the hcd may carry out minor adjustments on the frameinterval by writing a new value at each sof. this allows the hc to synchronize with an external clock resource and to adjust any unknown clock offset. code (hex): 0d read code (hex): 8d write bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 19: hcinterruptdisable register: bit description bit symbol description 31 mie a logic 0 is ignored by the hc. a logic 1 disables interrupt generation due to events speci?ed in other bits of this register. this ?eld is set after a hardware or software reset. 30 to 7 - reserved 6 rhsc 0 ignore 1 disable interrupt generation due to root hub status change 5 fno 0 ignore 1 disable interrupt generation due to frame number over?ow 4ue 0 ignore 1 disable interrupt generation due to unrecoverable error 3rd 0 ignore 1 disable interrupt generation due to resume detect 2sf 0 ignore 1 disable interrupt generation due to start of frame 1 - reserved 0so 0 ignore 1 disable interrupt generation due to scheduling overrun table 20: hcfminterval register: bit allocation bit 31 30 29 28 27 26 25 24 symbol fit fsmps[14:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 45 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2.2 hcfmremaining register (r: 0eh) the hcfmremaining register is a 14-bit down counter showing the bit time remaining in the current frame. code (hex): 0e read bit 23 22 21 20 19 18 17 16 symbol fsmps[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved fi[13:8] reset 00101110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fi[7:0] reset 11011111 access r/w r/w r/w r/w r/w r/w r/w r/w table 21: hcfminterval register: bit description bit symbol description 31 fit frameintervaltoggle: the hcd toggles this bit whenever it loads a new value to frameinterval. 30 to 16 fsmps [14:0] fslargestdatapacket: speci?es a value which is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of data in bits which can be sent or received by the hc in a single transaction at any given time without causing a scheduling overrun. the ?eld value is calculated by the hcd. 15 to 14 - reserved 13 to 0 fi[13:0] frameinterval: speci?es the interval between two consecutive sofs in bit times. the default value is 11999. the hcd must save the current value of this ?eld before resetting the hc. setting the hostcontrollerreset ?eld of the hccommandstatus register will cause the hc to reset this ?eld to its default value. hcd may choose to restore the saved value upon completing the reset sequence. table 22: hcfmremaining register: bit allocation bit 31 30 29 28 27 26 25 24 symbol frt reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 46 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2.3 hcfmnumber register (r: 0fh) the hcfmnumber register is a 16-bit counter. it provides a timing reference for events happening in the hc and the hcd. the hcd may use the 16-bit value speci?ed in this register and generate a 32-bit frame number without requiring frequent access to the register. code (hex): 0f read bit 15 14 13 12 11 10 9 8 symbol reserved fr[13:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol fr[7:0] reset 00000000 access rrrrrrrr table 23: hcfmremaining register: bit description bit symbol description 31 frt frameremainingtoggle: this bit is loaded from the frameintervaltoggle ?eld of the hcfminterval register whenever frameremaining reaches 0. this bit is used by the hcd for synchronization between frameinterval and frameremaining. 30 to 14 - reserved 13 to 0 fr[13:0] frameremaining: this counter is decremented at each bit time. when it reaches zero, it is reset by loading the frameinterval value speci?ed in the hcfminterval register at the next bit time boundary. when entering the usboperational state, the hc reloads it with the content of the frameinterval part of the hcfminterval register and uses the updated value from the next sof. table 24: hcfmnumber register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol fn[15:8] reset 00000000 access rrrrrrrr
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 47 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2.4 hclsthreshold register (r/w: 11h/91h) the hclsthreshold register contains an 11-bit value used by the hc to determine whether to commit to the transfer of a maximum of 8-byte ls packet before eof. neither the hc nor the hcd is allowed to change this value. code (hex): 11 read code (hex): 91 write bit 7 6 5 4 3 2 1 0 symbol fn[7:0] reset 00000000 access rrrrrrrr table 25: hcfmnumber register: bit description bit symbol description 31 to 16 - reserved 15 to 0 fn[15:0] framenumber: this is incremented when hcfmremaining is reloaded. it rolls over to 0000h after ffffh. when the usboperational state is entered, this will be incremented automatically. the hc will set bit startofframe in the hcinterruptstatus register. table 26: hclsthreshold register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved lst[10:8] reset 00000110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lst[7:0] reset 00101000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 48 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3 hc root hub registers all registers included in this partition are dedicated to the usb root hub, which is an integral part of the hc although it is functionally a separate entity. the host controller driver (hcd) emulates usbd accesses to the root hub via a register interface. the hcd maintains many usb-de?ned hub features that are not required to be supported in hardware. for example, the hubs device, con?guration, interface, and endpoint descriptors, as well as some static ?elds of the class descriptor, are maintained only in the hcd. the hcd also maintains and decodes the root hubs device address as well as other minor operations more suited for software than hardware. the root hub registers were developed to match the bit organization and operation of typical hubs found in the system. four 32-bit registers have been de?ned: ? hcrhdescriptora ? hcrhdescriptorb ? hcrhstatus ? hcrhportstatus[1:ndp] each register is read and written as a dword. these registers are only written during initialization to correspond with the system implementation. the hcrhdescriptora and hcrhdescriptorb registers are writeable regardless of the hcs usb states. hcrhstatus and hcrhportstatus are writeable during the usboperational state only. 10.3.1 hcrhdescriptora register (r/w: 12h/92h) the hcrhdescriptora register is the ?rst register of two describing the characteristics of the root hub. reset values are implementation-speci?c (is). the descriptor length (11), descriptor type and hub controller current (0) ?elds of the hub class descriptor are emulated by the hcd. all other ?elds are located in registers hcrhdescriptora and hcrhdescriptorb. remark: is denotes an implementation-speci?c reset value for that ?eld. code (hex): 12 read code (hex): 92 write table 27: hclsthreshold register: bit description bit symbol description 31 to 11 - reserved 10 to 0 lst[10:0] lsthreshold: contains a value that is compared to the frameremaining ?eld before a low-speed transaction is initiated. the transaction is started only if frameremaining 3 this ?eld. the value is calculated by the hcd, which considers transmission and set-up overhead.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 49 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 28: hcrhdescriptora register: bit description bit 31 30 29 28 27 26 25 24 symbol potpgt[7:0] reset is is is is is is is is access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved nocp ocpm dt nps psm reset 0 0 0 is is 0 is is access r r r r/w r/w r r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved ndp[1:0] reset 000000isis access rrrrrrrr table 29: hcrhdescriptora register: bit description bit symbol description 31 to 24 potpgt [7:0] powerontopowergoodtime: this byte speci?es the duration hcd has to wait before accessing a powered-on port of the root hub. the unit of time is 2 ms. the duration is calculated as potpgt 2ms. 23 to 13 - reserved 12 nocp noovercurrentprotection: this bit describes how the overcurrent status for the root hub ports are reported. when this bit is cleared, the overcurrentprotectionmode ?eld speci?es global or per-port reporting. 0 overcurrent status is reported collectively for all downstream ports 1 no overcurrent reporting supported 11 ocpm overcurrentprotectionmode: this bit describes how the overcurrent status for the root hub ports is reported. at reset, this ?eld re?ects the same mode as powerswitchingmode. this ?eld is valid only if the noovercurrentprotection ?eld is cleared. 0 overcurrent status is reported collectively for all downstream ports 1 overcurrent status is reported on a per-port basis. on power-up, clear this bit and then set it to logic 1. 10 dt devicetype: this bit speci?es that the root hub is not a compound deviceit is not permitted. this ?eld should always read/write 0.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 50 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.2 hcrhdescriptorb register (r/w: 13h/93h) the hcrhdescriptorb register is the second register of two describing the characteristics of the root hub. these ?elds are written during initialization to correspond with the system implementation. reset values are implementation-speci?c (is). code (hex): 13 read code (hex): 93 write 9 nps nopowerswitching: this bit is used to specify whether power switching is supported or ports are always powered. when this bit is cleared, bit powerswitchingmode speci?es global or per-port switching. 0 ports are power switched 1 ports are always powered on when the hc is powered on 8 psm powerswitchingmode: this bit is used to specify how the power switching of the root hub ports is controlled. this ?eld is valid only if the nopowerswitching ?eld is cleared. 0 all ports are powered at the same time 1 each port is powered individually. this mode allows port power to be controlled by either the global switch or per-port switching. if bit portpowercontrolmask is set, the port responds to only port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). 7 to 2 - reserved 1 to 0 ndp[1:0] numberdownstreamports: these bits specify the number of downstream ports supported by the root hub. the maximum number of ports supported by the isp1160 is 2. table 29: hcrhdescriptora register: bit description continued bit symbol description table 30: hcrhdescriptorb register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset n/a n/a n/a n/a n/a n/a n/a n/a access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved ppcm[2:0] reset n/a n/a n/a n/a n/a is is is access rrrrrr/wr/wr/w bit 15 14 13 12 11 10 9 8 symbol reserved reset n/a n/a n/a n/a n/a n/a n/a n/a access rrrrrrrr
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 51 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.3 hcrhstatus register (r/w: 14h/94h) the hcrhstatus register is divided into two parts. the lower word of a dword represents the hub status ?eld and the upper word represents the hub status change ?eld. reserved bits should always be written as logic 0. code (hex): 14 read code (hex): 94 write bit 7 6 5 4 3 2 1 0 symbol reserved dr[2:0] reset n/a n/a n/a n/a n/a is is is access rrrrrr/wr/wr/w table 31: hcrhdescriptorb register: bit description bit symbol description 31 to 19 - reserved 18 to 16 ppcm[2:0] portpowercontrolmask: each bit indicates whether a port is affected by a global power control command when powerswitchingmode is set. when set, the ports power state is only affected by per-port power control (set/clearportpower). when cleared, the port is controlled by the global power switch (set/clearglobalpower). if the device is con?gured to global switching mode (powerswitchingmode = 0), this ?eld is not valid. bit 0 reserved bit 1 ganged-power mask on port #1 bit 2 ganged-power mask on port #2 15 to 3 - reserved 2 to 0 dr[2:0] deviceremovable: each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 0 reserved bit 1 device attached to port #1 bit 2 device attached to port #2 table 32: hcrhstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol crwe reserved reset 00000000 access wrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved ocic lpsc reset 00000000 access rrrrrrr/wr/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 52 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. bit 15 14 13 12 11 10 9 8 symbol drwe reserved reset 00000000 access r/wrrrrrrr bit 7 6 5 4 3 2 1 0 symbol reserved oci lps reset 00000000 access rrrrrrrr/w table 33: hcrhstatus register: bit description bit symbol description 31 crwe on write clearremotewakeupenable: writing a logic 1 clears deviceremovewakeupenable. writing a logic 0 has no effect. 30 to 18 - reserved 17 ocic overcurrentindicatorchange: this bit is set by hardware when a change has occurred to the oci ?eld of this register. the hcd clears this bit by writing a logic 1. writing a logic 0 has no effect. 16 lpsc on read localpowerstatuschange: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write setglobalpower: in global power mode (powerswitchingmode = 0), this bit is written to logic 1 to turn on power to all ports (clear portpowerstatus). in per-port power mode, it sets portpowerstatus only on ports whose bit portpowercontrolmask is not set. writing a logic 0 has no effect. 15 drwe on read deviceremotewakeupenable: this bit enables the bit connectstatuschange as a resume event, causing a state transition usbsuspend to usbresume and setting the resumedetected interrupt. 0 connectstatuschange is not a remote wake-up event 1 connectstatuschange is a remote wake-up event on write setremotewakeupenable: writing a logic 1 sets deviceremovewakeupenable. writing a logic 0 has no effect. 14 to 2 - reserved 1 oci overcurrentindicator: this bit reports overcurrent conditions when global reporting is implemented. when set, an overcurrent condition exists. when clear, all power operations are normal. if per-port overcurrent protection is implemented this bit is always logic 0. 0 lps on read localpowerstatus: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write clearglobalpower: in global power mode (powerswitchingmode = 0), this bit is written to logic 1 to turn off power to all ports (clear portpowerstatus). in per-port power mode, it clears portpowerstatus only on ports whose bit portpowercontrolmask is not set. writing a logic 0 has no effect.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 53 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.4 hcrhportstatus[1:2] (r/w [1]:15h/95h, [2]: 16h/96h) the hcrhportstatus[1:2] register is used to control and report port events on a per-port basis. numberdownstreamports represents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to re?ect the port status, whereas the upper word re?ects the status change bits. some status bits are implemented with special write behavior. if a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. reserved bits should always be written logic 0. code (hex): [1] = 15, [2] = 16 read code (hex): [1] = 95, [2] = 96 write table 34: hcrhportstatus[1:2] register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved prsc ocic pssc pesc csc reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved lsda pps reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved prs poci pss pes ccs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 35: hcrshportstatus[1:2] register: bit description bit symbol description 31 to 21 - reserved 20 prsc portresetstatuschange: this bit is set at the end of the 10 ms port reset signal. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 port reset is not complete 1 port reset is complete 19 ocic portovercurrentindicatorchange: this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when root hub changes the portovercurrentindicator bit. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 no change in portovercurrentindicator 1 portovercurrentindicator has changed
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 54 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18 pssc portsuspendstatuschange: this bit is set when the full resume sequence has been completed. this sequence includes the 20 s resume pulse, ls eop, and 3 ms resynchronization delay. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. this bit is also cleared when resetstatuschange is set. 0 resume is not completed 1 resume is completed 17 pesc portenablestatuschange: this bit is set when hardware events cause the portenablestatus bit to be cleared. changes from hcd writes do not set this bit. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 no change in portenablestatus 1 change in portenablestatus 16 csc connectstatuschange: this bit is set whenever a connect or disconnect event occurs. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared when a setportreset, setportenable, or setportsuspend write occurs, this bit is set to force the driver to reevaluate the connection status since these writes should not occur if the port is disconnected. 0 no change in currentconnectstatus 1 change in currentconnectstatus remark: if bit deviceremovable[ndp] is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15 to 10 - reserved 9 lsda on read lowspeeddeviceattached: this bit indicates the speed of the device connected to this port. when set, a low-speed device is connected to this port. when clear, a full-speed device is connected to this port. this ?eld is valid only when the currentconnectstatus is set. 0 full-speed device attached 1 low-speed device attached on write clearportpower: the hcd clears bit portpowerstatus by writing a logic 1 to this bit. writing a logic 0 has no effect. table 35: hcrshportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 55 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8 pps on read portpowerstatus: this bit re?ects the port power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. the hcd sets this bit by writing setportpower or setglobalpower. the hcd clears this bit by writing clearportpower or clearglobalpower. which power control switches are enabled is determined by powerswitchingmode. in the global switching mode (powerswitchingmode = 0), only set/clearglobalpower controls this bit. in per-port power switching (powerswitchingmode = 1), if bit portpowercontrolmask[ndp] for the port is set, only set/clearportpower commands are enabled. if the mask is not set, only set/clearglobalpower commands are enabled. when port power is disabled, currentconnectstatus, portenablestatus, portsuspendstatus, and portresetstatus should be reset. 0 port power is off 1 port power is on on write setportpower: the hcd writes a logic 1 to set bit portpowerstatus. writing a logic 0 has no effect. remark: this bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved 4 prs on read portresetstatus: when this bit is set by a write to setportreset, port reset signaling is asserted. when reset is completed, this bit is cleared when portresetstatuschange is set. this bit cannot be set if currentconnectstatus is cleared. 0 port reset signal is not active 1 port reset signal is active on write setportreset: the hcd sets the port reset signaling by writing a logic 1 to this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portresetstatus but instead sets connectstatuschange. this informs the driver that it attempted to reset a disconnected port. 3 poci on read portovercurrentindicator: this bit is valid only when the root hub is con?gured in such a way that overcurrent conditions are reported on a per-port basis. if per-port overcurrent reporting is not supported, this bit is set to logic 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always re?ects the overcurrent input signal. 0 no overcurrent condition 1 overcurrent condition detected (write) clearsuspendstatus: the hcd writes a logic 1 to initiate a resume. writing a logic 0 has no effect. a resume is initiated only if portsuspendstatus is set. table 35: hcrshportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 56 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2 pss on read portsuspendstatus: this bit indicates whether the port is suspended or in the resume sequence. it is set by a setsuspendstate write and cleared when portsuspendstatuschange is set at the end of the resume interval. this bit cannot be set if currentconnectstatus is cleared. this bit is also cleared when portresetstatuschange is set at the end of the port reset or when the hc is placed in the usbresume state. if an upstream resume is in progress, it should propagate to the hc. 0 port is not suspended 1 port is suspended on write setportsuspend: the hcd sets bit portsuspendstatus by writing a logic 1 to this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portsuspendstatus; instead it sets connectstatuschange. this informs the driver that it attempted to suspend a disconnected port. 1 pes on read portenablestatus: this bit indicates whether the port is enabled or disabled. the root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. this change also causes portenabledstatuschange to be set. the hcd sets this bit by writing setportenable and clears it by writing clearportenable. this bit cannot be set when currentconnectstatus is cleared. this bit is also set at the completion of a port reset when resetstatuschange is set or port is suspended when suspendstatuschange is set. 0 port is disabled 1 port is enabled on write setportenable: the hcd sets portenablestatus by writing a logic 1. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portenablestatus, but instead sets connectstatuschange. this informs the driver that it attempted to enable a disconnected port. 0 ccs on read currentconnectstatus: this bit re?ects the current state of the downstream port. 0 no device connected 1 device connected on write clearportenable: the hcd writes a logic 1 to this bit to clear bit portenablestatus. writing a logic 0 has no effect. currentconnectstatus is not affected by any write. remark: this bit always reads logic 1 when the attached device is nonremovable (deviceremoveable[ndp]). table 35: hcrshportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 57 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4 hc dma and interrupt control registers 10.4.1 hchardwarecon?guration register (r/w: 20h/a0h) code (hex): 20 read code (hex): a0 write table 36: hchardwarecon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved 2_down stream port15k resistorsel suspend clknotstop analogoc enable reserved dackmode reset 00000 000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol eotinput polarity dackinput polarity dreq output polarity databuswidth[1:0] interrupt output polarity interrupt pintrigger interruptpin enable reset 00101 000 access r/w r/w r/w r/w r/w r/w r/w r/w table 37: hchardwarecon?guration register: bit description bit symbol description 15 to 13 - reserved 12 2_downstreamport15k resistorsel 0 use external 15 k w resistors for downstream ports 1 use built-in resistors for downstream ports 11 suspendclknotstop 0 clock can be stopped 1 clock can not be stopped 10 analogocenable 0 use external oc detection; digital input 1 use on-chip oc detection; analog input 9 - reserved 8 dackmode 0 normal operation; pin dack_n is used with read and write signals 1 reserved 7 eotinputpolarity 0 active low 1 active high 6 dackinputpolarity 0 active low 1 reserved 5 dreqoutputpolarity 0 active low 1 active high 4 to 3 databuswidth[1:0] these bits are ?xed at logic 0 and logic 1 for the isp1160. 01 16 bits others reserved
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 58 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.2 hcdmacon?guration register (r/w: 21h/a1h) code (hex): 21 read code (hex): a1 write 2 interruptoutputpolarity 0 active low 1 active high 1 interruptpintrigger 0 interrupt is level-triggered 1 interrupt is edge-triggered 0 interruptpinenable this bit is used as pin ints master interrupt enable and should be used together with register hc m pinterruptenable to enable pin int. 0 pin int is disabled 1 pin int is enabled table 37: hchardwarecon?guration register: bit description continued bit symbol description table 38: hcdmacon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved burstlen[1:0] dma enable reserved dma counter select itl_atl_ dataselect dmaread writeselect reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 39: hcdmacon?guration register: bit description bit symbol description 15 to 7 - reserved 6 to 5 burstlen[1:0] 00 single-cycle burst dma 01 4-cycle burst dma 10 8-cycle burst dma 11 reserved 4 dmaenable 0 dma is terminated 1 dma is enabled this bit will be reset to logic 0 when dma transfer is completed. 3 - reserved
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 59 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.3 hctransfercounter register (r/w: 22h/a2h) this register holds the number of bytes of a pio or dma transfer. for a pio transfer, the number of bytes being read or written to the isochronous transfer list (itl) or acknowledged transfer list (atl) buffer ram must be written into this register. for a dma transfer, the number of bytes must be written into this register as well. however, for this counter to be read into the dma counter, the hcd must set bit 2 (dmacounterselect) of the hcdmacon?guration register. the counter value for atl must not be greater than 1000h, and for itl it must not be greater than 800h. when the byte count of the data transfer reaches this value, the hc will generate an internal eot signal to set bit 2 (alleotinterrupt) of the hc m pinterrupt register, and also update the hcbufferstatus register. code (hex): 22 read code (hex): a2 write 10.4.4 hc m pinterrupt register (r/w: 24h/a4h) all the bits in this register will be active on power-on reset. however, none of the active bits will cause an interrupt on the interrupt pin (int) unless they are set by the respective bits in the hc m pinterruptenable register, and together with bit 0 of the hchardwarecon?guration register. 2 dmacounter select 0 dma counter not used. external eot must be used 1 enables the dma counter for dma transfer. hctransfercounter register must be ?lled with non-zero values for dreq to be raised after bit dma enable is set. 1 itl_atl_ dataselect 0 itl buffer ram selected for itl data 1 atl buffer ram selected for atl data 0 dmaread writeselect 0 read from the hc fifo buffer ram 1 write to the hc fifo buffer ram table 39: hcdmacon?guration register: bit description continued bit symbol description table 40: hctransfercounter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol counter value reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol counter value reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 41: hctransfercounter register: bit description bit symbol description 15 to 0 counter value the number of data bytes to be read to or written from ram.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 60 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. after this register (24h to read) is read, the bits that are active will not be reset, until logic 1 is written to the bits in this register (a4h to write) to clear it. to clear all the enabled bits in this register, the hcd must write ffh to this register. code (hex): 24 read code (hex): a4 write table 42: hc m pinterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved clkready hc suspended opr_reg reserved aiieot interrupt atlint sofitlint reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 43: hc m pinterrupt register: bit description bit symbol description 15 to 7 - reserved 6 clkready 0 no event 1 clock is ready. after a wake-up is sent, there is a wait for clock ready. maximum is 1 ms, and typical is 160 m s. 5hc suspended 0 no event 1 the hc has been suspended and no usb activity is sent from the microprocessor for each ms. when the microprocessor wants to suspend the hc, the microprocessor must write to the hccontrol register. and when all downstream devices are suspended, then the hc stops sending sof; the hc is suspended by having the hccontrol register written into. 4 opr_reg 0 no event 1 there are interrupts from hc side. need to read hccontrol and hcinterrupt registers to detect type of interrupt on the hc (if the hc requires the operational register to be updated). 3 - reserved
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 61 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.5 hc m pinterruptenable register (r/w: 25h/a5h) the bits 6:0 in this register are the same as those in the hc m pinterrupt register. they are used together with bit 0 of the hchardwarecon?guration register to enable or disable the bits in the hc m pinterrupt register. on power-on, all bits in this register are masked with logic 0. this means no interrupt request output on the interrupt pin int can be generated. when the bit is set to logic 1, the interrupt for the bit is not masked but enabled. code (hex): 25 read code (hex): a5 write 2 alleot interrupt 0 no event 1 implies that data transfer has been completed via pio transfer or dma transfer. occurrence of internal or external eot will set this bit. 1 atlint 0 no event 1 implies that the microprocessor must read atl data from the hc. this requires that the hcbufferstatus register must ?rst be read. the time for this interrupt depends on the number of clocks bit set for usb activities in each ms. 0 sofitlint 0 no event 1 implies that sof indicates the 1 ms mark. the itl buffer that the hc has handled must be read. to know the itl buffer status, the hcbufferstatus register must ?rst be read. this is for the microprocessor to get iso data to or from the hc. for more information, see the 6th paragraph in section 9.5 . table 43: hc m pinterrupt register: bit description continued bit symbol description table 44: hc m pinterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved clkready hc suspended enable opr interrupt enable reserved eot interrupt enable at l interrupt enable sof interrupt enable reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 62 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.5 hc miscellaneous registers 10.5.1 hcchipid register (r: 27h) read this register to get the id of the isp1160 silicon chip. the higher byte stands for the product name. the lower byte indicates the revision number of the product including engineering samples. code (hex): 27 read [1] x is logic 0 for isp1160bd and isp1160bm; x is logic 1 for isp1160bd/01 and isp1160bm/01. table 45: hc m pinterruptenable register: bit description bit symbol description 15 to 7 - reserved 6 clkready 0 power-up value 1 enables clkready interrupt 5hc suspended enable 0 power-up value 1 enables hc suspended interrupt. when the microprocessor wants to suspend the hc, the microprocessor must write to the hccontrol register. and when all downstream devices are suspended, then the hc stops sending sof; the hc is suspended by having the hccontrol register written into. 4 opr interrupt enable 0 power-up value 1 enables the 32-bit operational registers interrupt (if the hc requires the operational register to be updated) 3 - reserved 2eot interrupt enable 0 power-up value 1 enables the eot interrupt which indicates an end of a read/write transfer 1atl interrupt enable 0 power-up value 1 enables atl interrupt. the time for this interrupt depends on the number of clock bits set for usb activities in each ms. 0 sof interrupt enable 0 power-up value 1 enables the interrupt bit due to sof (for the microprocessor dma to get iso data from the hc by ?rst accessing the hcdmacon?guration register) table 46: hcchipid register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipid[15:8] reset 01100001 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol chipid[7:0] reset 0010001x [1] access rrrrrrrr
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 63 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.5.2 hcscratch register (r/w: 28h/a8h) this register is for the hcd to save and restore values when required. code (hex): 28 read code (hex): a8 write 10.5.3 hcsoftwarereset register (w: a9h) this register provides a means for software reset of the hc. to reset the hc, the hcd must write a reset value of f6h to this register. upon receiving the reset value, the hc resets all the registers except its buffer memory. code (hex): a9 write table 47: hcchipid register: bit description bit symbol description 15 to 0 chipid[15:0] isp1160s chip id table 48: hcscratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol scratch[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol scratch[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 49: hcscratch register: bit description bit symbol description 15 to 0 scratch[15:0] scratch register value table 50: hcsoftwarereset register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reset[15:8] reset 00000000 access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol reset[7:0] reset 00000000 access wwwwwwww table 51: hcsoftwarereset register: bit description bit symbol description 15 to 0 reset[15:0] writing a reset value of f6h will cause the hc to reset all the registers except its buffer memory.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 64 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6 hc buffer ram control registers 10.6.1 hcitlbufferlength register (r/w: 2ah/aah) write to this register to assign the itl buffer size in bytes: itl0 and itl1 are assigned the same value. for example, if hcitlbufferlength register is set to 2 kbytes, then itl0 and itl1 would be allocated 2 kbytes each. must follow the formula: atl buffer length + 2 (itl buffer size) 1000h (that is, 4 kbytes) where: itl buffer size = itl0 buffer length = itl1 buffer length. code (hex): 2a read code (hex): aa write 10.6.2 hcatlbufferlength register (r/w: 2bh/abh) write to this register to assign atl buffer size. code (hex): 2b read code (hex): ab write remark: the maximum total ram size is 1000h (4096 in decimal) bytes. that means itl0 (length) + itl1 (length) + atl (length) 1000h bytes. for example, if atl buffer length has been set to be 800h, then the maximum itl buffer length can only be set as 400h. table 52: hcitlbufferlength register: bit allocation bit 15 14 13 12 11 10 9 8 symbol itlbufferlength[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol itlbufferlength[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 53: hcitlbufferlength register: bit description bit symbol description 15 to 0 itlbufferlength[15:0] assign itl buffer length table 54: hcatlbufferlength register: bit allocation bit 15 14 13 12 11 10 9 8 symbol atlbufferlength[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 65 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6.3 hcbufferstatus register (r: 2ch) code (hex): 2c read 10.6.4 hcreadbackitl0length register (r: 2dh) this registers value stands for the current number of data bytes inside an itl0 buffer to be read back by the microprocessor. the hcd must set the hctransfercounter equivalent to this value before reading back the itl0 buffer ram. code (hex): 2d read bit 7 6 5 4 3 2 1 0 symbol atlbufferlength[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 55: hcatlbufferlength register: bit description bit symbol description 15 to 0 atlbufferlength[15:0] assign atl buffer length table 56: hcbufferstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol reserved atlbuffer done itl1buffer done itl0buffer done atlbuffer full itl1buffer full itl0buffer full reset 00000000 access rrrrrrrr table 57: hcbufferstatus register: bit description bit symbol description 15 to 6 - reserved 5 atlbuffer done 0 atl buffer not read by hc yet 1 atl buffer read by hc 4 itl1buffer done 0 itl1 buffer not read by hc yet 1 itl1 buffer read by hc 3 itl0buffer done 0 1tl0 buffer not read by hc yet 1 1tl0 buffer read by hc 2 atlbuffer full 0 atl buffer is empty 1 atl buffer is full 1 itl1buffer full 0 1tl1 buffer is empty 1 1tl1 buffer is full 0 itl0buffer full 0 itl0 buffer is empty 1 itl0 buffer is full
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 66 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6.5 hcreadbackitl1length register (r: 2eh) this registers value stands for the current number of data bytes inside the itl1 buffer to be read back by the microprocessor. the hcd must set the hctransfercounter equivalent to this value before reading back the itl1 buffer ram. code (hex): 2e read 10.6.6 hcitlbufferport register (r/w: 40h/c0h) this is the itl buffer ram read/write port. the bits 15:8 contain the data byte that comes from the itl buffer rams even address. the bits 7:0 contain the data byte that comes from the itl buffer rams odd address. code (hex): 40 read code (hex): c0 write table 58: hcreadbackitl0length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol rditl0bufferlength[15:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rditl0bufferlength[7:0] reset 00000000 access rrrrrrrr table 59: hcreadbackitl0length register: bit description bit symbol description 15 to 0 rditl0bufferlength[15:0] the number of bytes for itl0 data to be read back by the microprocessor table 60: hcreadbackitl1length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol rditl1bufferlength[15:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rditl1bufferlength[7:0] reset 00000000 access rrrrrrrr table 61: hcreadbackitl1length register: bit description bit symbol description 15 to 0 rditl1bufferlength[15:0] the number of bytes for itl1 data to be read back by the microprocessor.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 67 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. the hcd must set the byte count into the hctransfercounter register and check the hcbufferstatus register before reading from or writing to the buffer. the hcd must write the command (40h to read, c0h to write) once only, and then read or write both bytes of the data word. after every read/write, the pointer of itl buffer ram will be automatically increased by two to point to the next data word until it reaches the value of the hctransfercounter register; otherwise, an internal eot signal is not generated to set bit 2 (alleotinterrupt) of the hc m pinterrupt register and update the hcbufferstatus register. the hcd must take care of the fact that the internal buffer ram is organized in bytes. the hcd must write the byte count into the hctransfercounter register, but the hcd reads or writes the buffer ram by 16 bits (by 1 word). 10.6.7 hcatlbufferport register (r/w: 41h/c1h) this is the atl buffer ram read/write port. bits 15 to 8 contain the data byte that comes from the acknowledged transfer list (atl) buffer rams odd address. bits 7 to 0 contain the data byte that comes from the atl buffer rams even address. code (hex): 41 read code (hex): c1 write table 62: hcitlbufferport register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataword[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dataword[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 63: hcitlbufferport register: bit description bit symbol description 15 to 0 dataword[15:0] read/write itl buffer rams two data bytes. table 64: hcatlbufferport register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataword[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dataword[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 65: hcatlbufferport register: bit description bit symbol description 15 to 0 dataword[15:0] read/write atl buffer rams two data bytes.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 68 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. the hcd must set the byte count into the hctransfercounter register and check the hcbufferstatus register before reading from or writing to the buffer. the hcd must write the command (41h to read, c1h to write) once only, and then read or write both bytes of the data word. after every read/write, the pointer of atl buffer ram will be automatically increased by two to point to the next data word until it reaches the value of the hctransfercounter register; otherwise, an internal eot signal is not generated to set bit 2 (alleotinterrupt) of the hc m pinterrupt register and update the hcbufferstatus register. the hcd must take care of the difference: the internal buffer ram is organized in bytes, so the hcd must write the byte count into the hctransfercounter register, but the hcd reads or writes the buffer ram by 16 bits (by 1 data word).
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 69 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. power supply the isp1160 can operate at either 5 v or 3.3 v. when using 5 v as the isp1160s power supply input, only v cc (pin 56) can be connected to the 5 v power supply. an application with a 5 v power supply input is shown in figure 29 . the isp1160 has an internal dc/dc regulator to provide 3.3 v for its internal core. this internal 3.3 v can also be obtained from v reg(3v3) (pin 58). when using 3.3 v as the power supply input, the internal dc/dc regulator will be bypassed. all four power supply pins (v cc , v reg(3v3) , v hold1 and v hold2 ) can be used as power supply input. it is recommended that you connect all four power supply pins to the 3.3 v power supply, as shown in figure 30 . if, however, you have board space (routing area) constraints, you must connect at least v cc and v reg(3v3) to the 3.3 v power supply. for both 3.3 v and 5 v operation, all four power supply pins should be connected to a decoupling capacitor. 12. crystal oscillator the isp1160 has a crystal oscillator designed for a 6 mhz parallel-resonant crystal (fundamental). a typical circuit is shown in figure 31 . alternatively, an external clock signal of 6 mhz can be applied to input xtal1, while leaving output xtal2 open. see figure 32 . the 6 mhz oscillator frequency is multiplied to 48 mhz by an internal pll. fig 29. using a 5 v supply. fig 30. using a 3.3 v supply. 004aaa068 gnd v cc v reg(3v3) v hold1 v hold2 + 5 v isp1160 004aaa069 gnd v cc v reg(3v3) v hold1 v hold2 + 3.3 v isp1160 fig 31. oscillator circuit with external crystal. fig 32. oscillator circuit using external oscillator. 18 pf 6 mhz 18 pf 004aaa070 xtal2 xtal1 isp1160 osc out n.c. 6 mhz 004aaa071 xtal2 xtal1 isp1160 v cc
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 70 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. power-on reset (por) when v cc is directly connected to the reset_n pin, the internal pulse width (t porp ) will be typically (600 ns to 1000 ns) + x, when v cc is 3.3 v. the time x depends on how fast v cc is rising with respect to v trip (2.03 v). the time x is decided by the external power supply circuit. to give a better view of the functionality, figure 33 shows a possible curve of v cc(por) with dips at t2-t3 and t4-t5. if the dip at t4-t5 is too short (that is, <11 m s), the internal por pulse will not react and will remain low. the internal por starts with a 1 at t0. at t1, the detector will see the passing of the trip level and a delay element will add another t porp before it drops to 0. the internal por pulse will be generated whenever v cc(por) drops below v trip for more than 11 m s. even if v cc is 5.0 v, v trip still remains at 2.03 v. this is because the 5 v tolerant pads and on-chip voltage regulator ensure that 3.3 v is going to the internal por circuitry by clipping the voltage above 3.3 v. the reset_n pin can be either connected to v cc (using the internal por circuit) or externally controlled (by the microprocessor, asic, and so on). figure 34 shows the availability of the clock with respect to the external por. (1) porp = power-on reset pulse. fig 33. internal por timing. stable external clock is available at a. fig 34. clock with respect to the external por. 004aaa389 v bat(por) t0 t1 t2 t3 t4 t5 v trip t porp porp (1) t porp por external clock a 004aaa365
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 71 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. limiting values [1] equivalent to discharging a 100 pf capacitor via a 1.5 k w resistor (human body model). 15. recommended operating conditions [1] maximum value is 5 v tolerant. table 66: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(5v0) supply voltage to pin v cc - 0.5 + 6.0 v v cc(3v3) supply voltage to pin v reg(3v3) - 0.5 + 4.6 v v i input voltage - 0.5 + 6.0 v i lu latch-up current v i < 0 or v i >v cc - 100 ma v esd electrostatic discharge voltage i li <1 m a [1] - 2000 + 2000 v t stg storage temperature - 60 + 150 c table 67: recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage with internal regulator 4.0 5.0 5.5 v internal regulator bypass 3.0 3.3 3.6 v v i input voltage [1] 0v cc 5.5 v v i(ai/o) input voltage on analog i/o pins d + and d - 0 - 3.6 v v o(od) open-drain output pull-up voltage 0 - v cc v t amb ambient temperature - 40 - + 85 c
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 72 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. static characteristics [1] in the suspend mode, the minimum voltage is 2.7 v. [2] for details on power consumption, refer to philips application note an10022 isp1160x low power consumption . [1] not applicable for open-drain outputs. [2] the maximum and minimum values are applicable to transistor input only. the value will be different if internal pull-up or p ull-down resistors are used. table 68: static characteristics; supply pins v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd = 0 v; t amb =- 40 cto + 85 c; typical values at t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v cc = 5v v reg(3v3) internal regulator output [1] 3.0 3.3 3.6 v i cc operating supply current - 47 - ma i cc(susp ) suspend supply current - 40 500 m a v cc = 3.3 v i cc operating supply current - 50 - ma i cc(susp ) suspend supply current [2] - 150 500 m a table 69: static characteristics: digital pins v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd = 0 v; t amb =- 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage i ol = 4 ma - - 0.4 v i ol = 20 m a - - 0.1 v v oh high-level output voltage i oh = 4ma [1] 2.4 - - v i oh = 20 m av reg(3v3) - 0.1 - - v leakage current i li input leakage current [2] - 5- + 5 m a c in pin capacitance pin to gnd - - 5 pf open-drain outputs i oz off-state output current - 5- + 5 m a
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 73 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] d + is the usb positive data pin; d - is the usb negative data pin. [2] includes external resistors of 18 w 1 % on both pins h_d + and h_d - . table 70: static characteristics: analog i/o pins d + and d - v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd = 0 v; t amb =- 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(d + ) - v i(d - ) | [1] 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k w to + 3.6 v - - 0.3 v v oh high-level output voltage r l = 15 k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current - 10 - + 10 m a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance r pd pull-down resistance on hcs d + /d - enable internal resistors 10 - 20 k w z drv driver output impedance steady-state drive [2] 29 - 44 w z inp input impedance 10 - - m w
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 74 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. dynamic characteristics [1] dependent on the crystal oscillator start-up time. [1] excluding the ?rst transition from idle state. [2] characterized only, not tested. limits guaranteed by design. table 71: dynamic characteristics v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd = 0 v; t amb =- 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w(reset_n) pulse width on input reset_n crystal oscillator running 160 - - m s crystal oscillator stopped [1] ---ms crystal oscillator f xtal crystal frequency - 6 - mhz r s series resistance - - 100 w c load load capacitance c x1 , c x2 = 22 pf - 18 - pf external clock input t j external clock jitter - - 500 ps t duty clock duty cycle 45 50 55 % t cr , t cf rise time and fall time - - 3 ns table 72: dynamic characteristics: analog i/o pins d + and d - v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd = 0v;t amb =- 40 cto + 85 c; c l = 50 pf; see figure 42 for test circuit; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l = 50 pf; 90 % to 10 % of | v oh - v ol | 4 - 20 ns frfm differential rise/fall time matching (t fr / t ff ) [1] 90 - 111.11 % v crs output signal crossover voltage [1][2] 1.3 - 2.0 v
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 75 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17.1 programmed i/o timing table 73: dynamic characteristics: programmed interface timing symbol parameter conditions min typ max unit t as address set-up time before wr_n high 5--ns t ah address hold time after wr_n high 8 - - ns read timing t shsl ?rst rd_n/wr_n after a0 high 300 - - ns t slrl cs_n low to rd_n low 0 - - ns t rhsh rd_n high to cs_n high 0 - - ns t rlrh rd_n low pulse width 33 - - ns t rhrl rd_n high to next rd_n low 110 - - ns t rc rd_n cycle 143 - - ns t rhdz rd_n data hold time 3 - 22 ns t rldv rd_n low to data valid - - 32 ns write timing t wl wr_n low pulse width 26 - - ns t whwl wr_n high to next wr_n low 110 - - ns t wc wr_n cycle 136 - - ns t slwl cs_n low to wr_n low 0 - - ns t whsh wr_n high to cs_n high 0 - - ns t wdsu wr_n data set-up time 5 - - ns t wdh wr_n data hold time 8 - - ns
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 76 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17.2 dma timing 17.2.1 single-cycle dma timing [1] t dc =t rhal + t ds + t alrl fig 35. programmed interface timing. 004aaa367 a0 d [ 15:0 ] d [ 15:0 ] wr_n rd_n cs_n data valid data valid data valid data valid data valid data valid data valid data valid data valid t shsl t rlrh t rhrl t rldv t wl t whwl t wdh t wdsu t rc t wc t rhdz t slrl t rhsh t slwl t whsh t ah t as table 74: dynamic characteristics: single-cycle dma timing symbol parameter conditions min typ max unit read/write timing t rlrh rd_n pulse width 33 - - ns t rldv read process data set-up time 26 - - ns t rhdz read process data hold time 0 - 20 ns t wsu write process data set-up time 5 - - ns t whd write process data hold time 0 - - ns t ahrh dack_n high to dreq high 72 - - ns t alrl dack_n low to dreq low - - 21 ns t dc dreq cycle [1] ---ns t shah rd_n/wr_n high to dack_n high 0--ns t rhal dreq high to dack_n low 0 - - ns t ds dreq pulse spacing 146 - - ns
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 77 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17.2.2 burst mode dma timing [1] t dc =t slal + (4 or 8)t rc + t ds fig 36. single-cycle dma timing. 004aaa371 dreq dack_n d [ 15:0 ] (read) d [ 15:0 ] (write) rd_n or wr_n t ds t ahrh t dc data valid data valid t alrl t rhal t whd t wsu t rldv t rhdz t shah table 75: dynamic characteristics: burst mode dma timing symbol parameter conditions min typ max unit read/write timing (for 4-cycle and 8-cycle burst mode) t rlrh wr_n/rd_n low pulse width 42 - - ns t rhrl wr_n/rd_n high to next wr_n/rd_n low 60--ns t rc wr_n/rd_n cycle 102 - - ns t slrl rd_n/wr_n low to dreq low 22 - 64 ns t shah rd_n/wr_n high to dack_n high 0--ns t slal dreq high to dack_n low 0 - - ns t dc dreq cycle [1] ---ns t ds(read) dreq pulse spacing (read) 4-cycle burst mode 105 - - ns t ds(read) dreq pulse spacing (read) 8-cycle burst mode 150 - - ns t ds(write) dreq pulse spacing (write) 4-cycle burst mode 72 - - ns t ds(write) dreq pulse spacing (write) 8-cycle burst mode 167 - - ns t rlis rd_n/wr_n low to eot low 0 - - ns
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 78 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17.2.3 external eot timing for single-cycle dmasetup 17.2.4 external eot timing for burst mode dma fig 37. burst mode dma timing. 004aaa372 t rhrl t ds t rhsh dreq dack_n rd_n or wr_n t slrl t shah t rlrh t rc t slal fig 38. external eot timing for single-cycle dma. 004aaa373 dreq dack_n eot rd_n or wr_n t rlis > 0 ns fig 39. external eot timing for burst mode dma. 004aaa374 dreq dack_n eot t rlis > 0 ns rd_n or wr_n
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 79 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18. application information 18.1 typical interface circuit 18.2 interfacing a isp1160 to a sh7709 risc processor this section shows a typical interface circuit between the isp1160 and a risc processor. the hitachi sh-3 series risc processor sh7709 is used as the example. the main isp1160 signals to be taken into consideration for connecting to a sh7709 risc processor are: ? a 16-bit data bus: d[15:0] for the isp1160. the isp1160 is little endian compatible. ? the address line a0 is needed for a complete addressing of the isp1160 internal registers: C a0 = 0 will select the data port of the host controller C a0 = 1 will select the command port of the host controller ? the cs_n line is used for chip selection of the isp1160 in a certain address range of the risc system. this signal is active low. ? rd_n and wr_n are common read and write signals. these signals are active low. for mosfet, r dson = 150 m w . fig 40. typical interface circuit to hitachi sh-3 (sh7709) risc processor. 004aaa072 fb4 fb3 fb2 fb1 22 w (2 ) 22 pf 22 pf 47 pf (2 ) + 5 v + 3.3 v + 3.3 v + 5 v v dd + 5 v + 5 v vbus_dn2 vbus_dn1 + 3.3 v + 5 v sh7709 a1 a0 mosfet (2 ) usb downstream port #1 usb downstream port #2 d [ 15:0 ] d [ 15:0 ] dreq0 dreq dack0_n dack_n cs5 cs_n rd_n rd_n rd/wr_n wr_n eot ptc0 h_wakeup ptc1 h_suspend gnd xtal2 extal2 32 khz 6 mhz xtal extal dgnd agnd irq2 int rstout reset_n isp1160 clkout h_oc1_n h_oc2_n h_psw2_n h_psw1_n v cc v reg (3v3) v hold 1 v hold2 h_dm1 h_dp1 h_dm2 h_dp2 ndp_sel xtal2 xtal1 v reg v dd + 3.3 v 22 w (2 ) 47 pf (2 ) 7
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 80 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? there is a dma channel standard control line: dreq and dack_n. the dreq signal has programmable active levels. ? an interrupt line int is used by the hc. it has programmable level/edge and polarity (active high or low). ? the internal 15 k w pull-down resistors are used for the hcs two usb downstream ports. ? the reset_n signal is active low. remark: sh7709s system clock input is for reference only. refer to sh7709s speci?cation for its actual use. the isp1160 can work under either 3.3 v or 5.0 v power supply; however, its internal core works at 3.3 v. when using 3.3 v as the power supply input, the internal dc/dc regulator will be bypassed. it is best to connect all four power supply pins (v cc , v reg(3v3) , v hold1 and v hold2 ) to the 3.3 v power supply (for more information, see section 11 ). all of the isp1160s i/o pins are 5 v-tolerant. this feature allows the isp1160 the ?exibility to be used in an embedded system under either a 3.3 v or a 5 v power supply. a typical sh7709 interface circuit is shown in figure 40 . 18.3 typical software model this section shows a typical software requirement for an embedded system that incorporates the isp1160. the software model for a digital still camera (dsc) is used as the example for illustration (as shown in figure 41 ). the host stack provides api for class driver and device driver, both of which provide api for application tasks for host function.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 81 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 19. test information the dynamic characteristics of the analog i/o pins d + and d - as listed in ta b l e 7 2 were determined using the circuit shown in figure 42 . fig 41. the isp1160 software model for dsc application. printer flash card reader/ writer usb upstream usb downstream digital still camera risc rom ram isp1160 len control 004aaa073 mechanism control task image processing tasks file management os printer ui/control printing class driver host stack usb host stack class driver application layer device drivers mass storage class driver isp1160 hal full-speed mode: load capacitance c l = 50 pf. full-speed mode only: internal 1.5 k w pull-up resistor on pin d + . fig 42. load impedance. mgt967 15 k w 22 w test point c l 50 pf d.u.t.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 82 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20. package outline fig 43. lqfp64 (sot314-2) package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 83 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 44. lqfp64 (sot414-1) package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 7.1 6.9 0.4 9.15 8.85 0.64 0.36 7 0 o o 0.08 0.08 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot414-1 136e06 ms-026 00-01-19 03-02-20 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.64 0.36 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm sot414-1
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 84 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21. soldering 21.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 21.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 21.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 85 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 21.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 21.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 76: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors isp1160 embedded usb host controller product data rev. 05 24 december 2004 86 of 88 9397 750 13963 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 22. revision history table 77: revision history rev date cpcn description 05 20041224 200412019 product data (9397 750 13963) modi?cations: ? figure 2 pin con?guration lqfp64. : added a ?gure note. ? table 2 pin description lqfp64 : in the description for pin 60, changed address a1 to a2. ? section 9.8.1 using an internal oc detection circuit : fourth paragraph, second sentence, changed source to drain and drain to source. 04 20030704 - product data (9397 750 11371) 03 20030227 - product data (9397 750 10765) 02 20020912 - product data (9397 750 09628) 01 20020104 - objective data (9397 750 09161)
9397 750 13963 philips semiconductors isp1160 embedded usb host controller ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 05 24 december 2004 87 of 88 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 23. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 24. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 25. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 26. trademarks arm7 and arm9 are trademarks of arm ltd. goodlink is a trademark of koninklijke philips electronics n.v. hitachi is a registered trademark of hitachi ltd. mips-based is a trademark of mips technologies, inc. softconnect is a trademark of koninklijke philips electronics n.v. strongarm is a registered trademark of arm ltd. superh is a trademark of hitachi ltd. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 24 december 2004 document order number: 9397 750 13963 contents philips semiconductors isp1160 embedded usb host controller 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 8 7.1 pll clock multiplier. . . . . . . . . . . . . . . . . . . . . . 8 7.2 bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 analog transceivers . . . . . . . . . . . . . . . . . . . . . 8 7.4 philips serial interface engine (sie). . . . . . . . . 8 8 microprocessor bus interface. . . . . . . . . . . . . . 8 8.1 programmed i/o (pio) addressing mode . . . . . 8 8.2 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.3 control registers access by pio mode . . . . . . 10 8.4 fifo buffer ram access by pio mode . . . . . 11 8.5 fifo buffer ram access by dma mode. . . . . 12 8.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 host controller (hc) . . . . . . . . . . . . . . . . . . . . 16 9.1 hcs four usb states . . . . . . . . . . . . . . . . . . . 16 9.2 generating usb traf?c . . . . . . . . . . . . . . . . . . 17 9.3 ptd data structure . . . . . . . . . . . . . . . . . . . . . 19 9.4 hcs internal fifo buffer ram structure . . . . 22 9.5 hc operational model . . . . . . . . . . . . . . . . . . . 28 9.6 microprocessor loading. . . . . . . . . . . . . . . . . . 31 9.7 internal pull-down resistors for downstream ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.8 overcurrent detection and power switching control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9 suspend and wake-up . . . . . . . . . . . . . . . . . . 34 10 hc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 hc control and status registers . . . . . . . . . . . 37 10.2 hc frame counter registers. . . . . . . . . . . . . . . 44 10.3 hc root hub registers . . . . . . . . . . . . . . . . . . 48 10.4 hc dma and interrupt control registers . . . . . 57 10.5 hc miscellaneous registers . . . . . . . . . . . . . . 62 10.6 hc buffer ram control registers . . . . . . . . . . . 64 11 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 69 13 power-on reset (por) . . . . . . . . . . . . . . . . . . . 70 14 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 71 15 recommended operating conditions. . . . . . . 71 16 static characteristics. . . . . . . . . . . . . . . . . . . . 72 17 dynamic characteristics . . . . . . . . . . . . . . . . . 74 17.1 programmed i/o timing. . . . . . . . . . . . . . . . . . 75 17.2 dma timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18 application information . . . . . . . . . . . . . . . . . 79 18.1 typical interface circuit . . . . . . . . . . . . . . . . . . 79 18.2 interfacing a isp1160 to a sh7709 risc processor. . . . . . . . . . . . . . . . . . . . . . . 79 18.3 typical software model . . . . . . . . . . . . . . . . . . 80 19 test information. . . . . . . . . . . . . . . . . . . . . . . . 81 20 package outline . . . . . . . . . . . . . . . . . . . . . . . . 82 21 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 21.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 21.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 84 21.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 84 21.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 85 21.5 package related soldering information . . . . . . 85 22 revision history . . . . . . . . . . . . . . . . . . . . . . . 86 23 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 87 24 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 25 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 26 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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